Publications

Google Scholar and DBLP

2013

• Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and Onur Mutlu,
  "An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms"
  Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.
• Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
  "Utility-Based Acceleration of Multithreaded Applications on Asymmetric CMPs,"
  Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.
• Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, and Chita R. Das,
  "Orchestrated Scheduling and Prefetching for GPGPUs,"
  Proceedings of the 40th International Symposium on Computer Architecture (ISCA), Tel-Aviv, Israel, June 2013.
• Asit K. Mishra, Onur Mutlu, and Chita R. Das,
  "A Heterogeneous Multiple Network-on-Chip Design: An Application-Aware Approach,"
  Proceedings of the 50th Design Automation Conference (DAC), Austin, TX, June 2013.
• Onur Mutlu,
  "Memory Scaling: A Systems Architecture Perspective,"
  Proceedings of the 5th International Memory Workshop (IMW), Monterey, CA, May 2013.
• Alexey Tumanov, Joshua Wise, Onur Mutlu, and Gregory R. Ganger,
  "Asymmetry-Aware Execution Placement on Manycore Chips,"
  Proceedings of the 3rd Workshop on Systems for Future Multicore Architectures (SFMA), Prague, Czech Republic, April 2013. Slides (pdf)
  
• Emre Kultursay, Mahmut Kandemir, Anand Sivasubramaniam, and Onur Mutlu,
  "Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative"
  Proceedings of the 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, April 2013.
• Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai,
  "Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis and Modeling"
  Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Grenoble, France, March 2013. Slides (ppt)
• Adwait Jog, Onur Kayiran, Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar Iyer, and Chita R. Das,
  "OWL: Cooperative Thread Array Aware Scheduling Techniques for Improving GPGPU Performance"
  Proceedings of the 18th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Houston, TX, March 2013. Slides (pptx)
• Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu,
  "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture"
  Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), Shenzhen, China, February 2013. Slides (pptx)
• Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, and Onur Mutlu,
  "MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems"
  Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), Shenzhen, China, February 2013. Slides (pptx)
• Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, and Mani Azimi,
  "Application-to-Core Mapping Policies to Reduce Memory System Interference in Multi-Core Systems"
  Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), Shenzhen, China, February 2013. Slides (pptx)
• Hongyi Xin, Donghyuk Lee, Farhad Hormozdiari, Samihan Yedkar, Onur Mutlu, and Can Alkan,
  "Accelerating Read Mapping with FastHASH"
  BMC Genomics, 14(Suppl 1):S13, 21 January 2013. PDF article
  also appears in Proceedings of the 11th Asia Pacific Bioinformatics Conference (APBC), Vancouver, BC, Canada, January 2013. Slides (pptx)

2012

• Onur Mutlu,
  "Message from the Micro-45 Program Chair"
  Proceedings of the 45th International Symposium on Microarchitecture (MICRO), Vancouver, BC, Canada, December 2012. Slides (pdf)
  

• Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, and Onur Mutlu,
  "HAT: Heterogeneous Adaptive Throttling for On-Chip Networks"
  Proceedings of the 24th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), New York, NY, October 2012. Slides (pptx) (pdf)
  

• HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, and Onur Mutlu,
  "Row Buffer Locality Aware Caching Policies for Hybrid Memories"
  Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), Montreal, Quebec, Canada, September 2012. Slides (pptx) (pdf)
  Best paper award (in Computer Systems and Applications track).
• Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrian Cristal, Osman Unsal, and Ken Mai,
  "Flash Correct-and-Refresh: Retention-Aware Error Management for Increased Flash Memory Lifetime"
  Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), Montreal, Quebec, Canada, September 2012. Slides (ppt) (pdf)
  
• Justin Meza, Jing Li, and Onur Mutlu,
  "A Case for Small Row Buffers in Non-Volatile Main Memories"
  Proceedings of the 30th IEEE International Conference on Computer Design (ICCD) Poster Session, Montreal, Quebec, Canada, September 2012. Poster (pdf) Poster (ppt)
  
• Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu, Philip B. Gibbons, Michael A. Kozuch, and Todd C. Mowry,
  "Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches"
  Proceedings of the 21st ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, September 2012. Slides (pptx)
  
• Vivek Seshadri, Onur Mutlu, Michael A. Kozuch, and Todd C. Mowry,
  "The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing"
  Proceedings of the 21st ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), Minneapolis, MN, September 2012. Slides (pptx)
  
• Reetuparna Das, Rachata Ausavarungnirun, Onur Mutlu, Akhilesh Kumar, and Mani Azimi,
  "Application-to-Core Mapping Policies to Reduce Memory Interference in Multi-Core Systems"
  Proceedings of the 21st ACM International Conference on Parallel Architectures and Compilation Techniques (PACT) Poster Session, Minneapolis, MN, September 2012. Poster (pdf) Poster (pptx)
  
• Nachiappan Chidambaram Nachiappan, Asit K. Mishra, Mahmut Kandemir, Anand Sivasubramaniam, Onur Mutlu, and Chita R. Das,
  "Application-aware Prefetch Prioritization in On-chip Networks"
  Proceedings of the 21st ACM International Conference on Parallel Architectures and Compilation Techniques (PACT) Poster Session, Minneapolis, MN, September 2012.
  
• Gennady Pekhimenko, Todd C. Mowry, Onur Mutlu,
  "Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency"
  Proceedings of the 21st ACM International Conference on Parallel Architectures and Compilation Techniques (PACT) Student Research Competition, Minneapolis, MN, September 2012. Poster (pdf) Poster (pptx) Slides (pdf) Slides (pptx)
  
• George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu, and Srinivasan Seshan,
  "On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-core Interconnects"
  Proceedings of the 2012 ACM SIGCOMM Conference (SIGCOMM), Helsinki, Finland, August 2012. Slides (pptx)
  
• Jamie Liu, Ben Jaiyen, Richard Veras, and Onur Mutlu,
  "RAIDR: Retention-Aware Intelligent DRAM Refresh"
  Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012. Slides (pdf)
  
• Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu,
  "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM"
  Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012. Slides (pptx)
  
• Rachata Ausavarungnirun, Kevin Chang, Lavanya Subramanian, Gabriel Loh, and Onur Mutlu,
  "Staged Memory Scheduling: Achieving High Performance and Scalability in Heterogeneous Systems"
  Proceedings of the 39th International Symposium on Computer Architecture (ISCA), Portland, OR, June 2012. Slides (pptx)
  
• Onur Mutlu,
  "Message from the MSPC 2012 Program Chair"
  Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness (MSPC), Beijing, China, June 2012. Slides (pdf)
  

• Boris Grot, Joel Hestness, Stephen W. Keckler, and Onur Mutlu,
  "A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips"
  IEEE Micro, Special Issue: Micro's Top Picks from 2011 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 32, No. 3, May/June 2012.
• Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Chang, Rachata Ausavarungnirun, and Onur Mutlu,
  "MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect"
  Proceedings of the 6th ACM/IEEE International Symposium on Networks on Chip (NOCS), Lyngby, Denmark, May 2012. Slides (pptx) (pdf)
  One of the five papers nominated for the Best Paper Award by the Program Committee.
• Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
  "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems"
  ACM Transactions on Computer Systems (TOCS), April 2012.
  A previous version as HPS Technical Report, TR-HPS-2012-001, February 2012.
• Yu Cai, Erich F. Haratsch, Onur Mutlu, and Ken Mai,
  "Error Patterns in MLC NAND Flash Memory: Measurement, Characterization, and Analysis"
  Proceedings of the Design, Automation, and Test in Europe Conference (DATE), Dresden, Germany, March 2012. Slides (ppt)
• Jose A. Joao, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
  "Bottleneck Identification and Scheduling in Multithreaded Applications"
  Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), London, UK, March 2012. Slides (ppt) (pdf)
• Justin Meza, Jichuan Chang, HanBin Yoon, Onur Mutlu, and Parthasarathy Ranganathan,
  "Enabling Efficient and Scalable Hybrid Memories Using Fine-Granularity DRAM Cache Management"
  IEEE Computer Architecture Letters (CAL), February 2012.
• Onur Mutlu,
  "Some Ideas and Principles for Achieving Higher System Energy Efficiency"
  Presented at the NSF Workshop on Cross-Layer Power Optimization and Management (NSF CPOM), Los Angeles, CA, February 2012.
  Slides (ppt)
• Hongyi Xin, Donghyuk Lee, Farhad Hormozdiari, Can Alkan, and Onur Mutlu,
  "FastHASH: A New GPU-friendly Algorithm for Fast and Comprehensive Next-generation Sequence Mapping"
  Pacific Symposium on Biocomputing (PSB) Poster Session, Hawaii, January 2012. Poster (pdf) Abstract (pdf) Slides (pdf)

2011

• Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda,
  "Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning"
  Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011. Slides (pptx)
  

• Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
  "Parallel Application Memory Scheduling"
  Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011. Slides (pptx)
  

• Veynu Narasiman, Chang Joo Lee, Michael Shebanow, Rustam Miftakhutdinov, Onur Mutlu, and Yale N. Patt,
  "Improving GPU Performance via Large Warps and Two-Level Warp Scheduling"
  Proceedings of the 44th International Symposium on Microarchitecture (MICRO), Porto Alegre, Brazil, December 2011. Slides (ppt)
  A previous version as HPS Technical Report, TR-HPS-2010-006, December 2010.
• Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,
  "Prefetch-Aware Memory Controllers"
  IEEE Transactions on Computers (TC), Vol. 60, No. 10, pages 1406-1430, October 2011.
• Vivek Seshadri, Onur Mutlu, Todd Mowry, and Michael A. Kozuch
  "Improving Cache Performance Using Victim Tag Stores"
  SAFARI Technical Report, TR-SAFARI-2011-009, Carnegie Mellon University, September 2011.
• Chris Fallin, Xiangyao Yu, Greg Nazario, and Onur Mutlu,
  "A High-Performance Hierarchical Ring On-Chip Interconnect with Low-Cost Routers"
  SAFARI Technical Report, TR-SAFARI-2011-007, Carnegie Mellon University, September 2011.
• Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, and Onur Mutlu,
  "Adaptive Cluster Throttling: Improving High-Load Performance in Bufferless On-Chip Networks"
  SAFARI Technical Report, TR-SAFARI-2011-006, Carnegie Mellon University, September 2011.
• HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael Harding, and Onur Mutlu,
  "Row Buffer Locality-Aware Data Placement in Hybrid Memories"
  SAFARI Technical Report, TR-SAFARI-2011-005, Carnegie Mellon University, September 2011.
• Chris Craik and Onur Mutlu,
  "Investigating the Viability of Bufferless NoCs in Modern Chip Multi-Processor Systems"
  SAFARI Technical Report, TR-SAFARI-2011-004, Carnegie Mellon University, August 2011.
• George Nychis, Chris Fallin, Thomas Moscibroda, Srinivasan Seshan, and Onur Mutlu,
  "Congestion Control for Scalability in Bufferless On-Chip Networks"
  SAFARI Technical Report, TR-SAFARI-2011-003, Carnegie Mellon University, July 2011.
• Boris Grot, Joel Hestness, Stephen W. Keckler, and Onur Mutlu,
  "Kilo-NOC: A Heterogeneous Network-on-Chip Architecture for Scalability and Service Guarantees"
  Proceedings of the 38th International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011. Slides (pptx)
  One of the 12 computer architecture papers of 2011 selected as Top Picks by IEEE Micro.
  
• Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
  "Prefetch-Aware Shared Resource Management for Multi-Core Systems"
  Proceedings of the 38th International Symposium on Computer Architecture (ISCA), San Jose, CA, June 2011. Slides (pptx)
  
• Howard David, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, and Onur Mutlu,
  "Memory Power Management via Dynamic Voltage/Frequency Scaling"
  Proceedings of the 8th International Conference on Autonomic Computing (ICAC), Karlsruhe, Germany, June 2011. Slides (pptx) (pdf)
  
• Michael Papamichael, James C. Hoe, and Onur Mutlu,
  "FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations"
  Proceedings of the 5th ACM/IEEE International Symposium on Networks on Chip (NOCS), Pittsburgh, PA, May 2011. Slides (pdf)

• Reetuparna Das, Onur Mutlu, Akhilesh Kumar, and Mani Azimi,
  "Application-to-Core Mapping Policies to Reduce Interference in On-Chip Networks"
  SAFARI Technical Report, TR-SAFARI-2011-001, Carnegie Mellon University, May 2011.
• Chris Fallin, Chris Craik, and Onur Mutlu,
  "CHIPPER: A Low-Complexity Bufferless Deflection Router"
  Proceedings of the 17th International Symposium on High-Performance Computer Architecture (HPCA), pages 144-155, San Antonio, TX, February 2011. Slides (pptx)
  An extended version as SAFARI Technical Report, TR-SAFARI-2010-001, Carnegie Mellon University, December 2010.
• Yale N. Patt and Onur Mutlu,
  "Top Picks: Guest Editors' Introduction"
  IEEE Micro, Special Issue: Micro's Top Picks from 2010 Computer Architecture Conferences (IEEE MICRO), Vol. 31, No. 1, pages 6-10, January/February 2011.
• M. Aater Suleman, Onur Mutlu, Jose A. Joao, Khubaib, and Yale N. Patt,
  "Data Marshaling for Multi-core Systems"
  IEEE Micro, Special Issue: Micro's Top Picks from 2010 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 31, No. 1, pages 56-64, January/February 2011.
• Reetuparna Das, Onur Mutlu, Thomas Moscibroda, and Chita R. Das,
  "Aergia: A Network-on-Chip Exploiting Packet Latency Slack"
  IEEE Micro, Special Issue: Micro's Top Picks from 2010 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 31, No. 1, pages 29-41, January/February 2011.
• Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter,
  "Thread Cluster Memory Scheduling"
  IEEE Micro, Special Issue: Micro's Top Picks from 2010 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 31, No. 1, pages 78-89, January/February 2011.

2010

• Yoongu Kim, Michael Papamichael, Onur Mutlu, and Mor Harchol-Balter,
  "Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior"
  Proceedings of the 43rd International Symposium on Microarchitecture (MICRO), pages 65-76, Atlanta, GA, December 2010. Slides (pptx) (pdf)
  One of the 11 computer architecture papers of 2010 selected as Top Picks by IEEE Micro.
• George Nychis, Chris Fallin, Thomas Moscibroda, and Onur Mutlu,
  "Next Generation On-Chip Networks: What Kind of Congestion Control Do We Need?"
  Proceedings of the 9th ACM Workshop on Hot Topics in Networks (HOTNETS), Monterey, CA, October 2010. Slides (ppt) (key)
  
• Tanausu Ramirez, Alex Pajuelo, Oliverio Santana, Onur Mutlu, and Mateo Valero,
  "Efficient Runahead Threads"
  Proceedings of the 19th ACM International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 443-452, Vienna, Austria, September 2010. Slides (pdf)
  
• Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger,
  "Phase Change Memory Architecture and the Quest for Scalability"
  Communications of the ACM (CACM), Research Highlight, Vol. 53, No. 7, pages 99-106, July 2010.

• Reetuparna Das, Onur Mutlu, Thomas Moscibroda, and Chita R. Das,
  "Aergia: Exploiting Packet Latency Slack in On-Chip Networks"
  Proceedings of the 37th International Symposium on Computer Architecture (ISCA), pages 106-116, Saint-Malo, France, June 2010. Slides (pptx)
  One of the 11 computer architecture papers of 2010 selected as Top Picks by IEEE Micro.
• M. Aater Suleman, Onur Mutlu, Jose A. Joao, Khubaib, and Yale N. Patt,
  "Data Marshaling for Multi-core Architectures"
  Proceedings of the 37th International Symposium on Computer Architecture (ISCA), pages 441-450, Saint-Malo, France, June 2010. Slides (ppt)
  One of the 11 computer architecture papers of 2010 selected as Top Picks by IEEE Micro.
• Boris Grot, Stephen W. Keckler, and Onur Mutlu,
  "Topology-aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors"
  Proceedings of the 6th Annual Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA), Saint-Malo, France, June 2010. Slides (pptx)

• Paul Bogdan, Miray Kas, Radu Marculescu, and Onur Mutlu,
  "QuaLe: A Quantum-Leap Inspired Model for Non-Stationary Analysis of NoC Traffic in Multi-Processor Platforms"
  Proceedings of the 4th ACM/IEEE International Symposium on Networks on Chip (NOCS), pages 241-248, Grenoble, France, May 2010.

• Yanjing Li, Onur Mutlu, Donald S. Gardner, and Subhasish Mitra,
  "Concurrent Autonomous Self-Test for Uncore Components in System-on-Chips"
  Proceedings of the 28th IEEE VLSI Test Symposium (VTS), pages 232-237, Santa Cruz, CA, April 2010. Slides (ppt)
  Best paper award.
• Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
  "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems"
  HPS Technical Report, TR-HPS-2010-002, April 2010.
• Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
  "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems"
  Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 335-346, Pittsburgh, PA, March 2010. Slides (pdf)
  Best paper award.
• Yoongu Kim, Dongsu Han, Onur Mutlu, and Mor Harchol-Balter,
  "ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers"
  Proceedings of the 16th International Symposium on High-Performance Computer Architecture (HPCA), Bangalore, India, January 2010. Slides (pptx)
  Best paper session. One of the four papers nominated for the Best Paper Award by the Program Committee.
• Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, and Doug Burger,
  "Phase Change Technology and the Future of Main Memory"
  IEEE Micro, Special Issue: Micro's Top Picks from 2009 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 30, No. 1, pages 60-70, January/February 2010.
• M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt,
  "Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures"
  IEEE Micro, Special Issue: Micro's Top Picks from 2009 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 30, No. 1, pages 131-141, January/February 2010.

2009

• Reetuparna Das, Onur Mutlu, Thomas Moscibroda, and Chita R. Das,
  "Application-Aware Prioritization Mechanisms for On-Chip Networks"
  Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), pages 280-291, New York, NY, December 2009. Slides (pptx)
  
• Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, and Yale N. Patt,
  "Coordinated Control of Multiple Prefetchers in Multi-Core Systems"
  Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), pages 316-326, New York, NY, December 2009. Slides (ppt)
  
• Boris Grot, Stephen W. Keckler, and Onur Mutlu,
  "Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip"
  Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), pages 268-279, New York, NY, December 2009. Slides (pdf)
  
• Chang Joo Lee, Veynu Narasiman, Onur Mutlu, and Yale N. Patt,
  "Improving Memory Bank-Level Parallelism in the Presence of Prefetching"
  Proceedings of the 42nd International Symposium on Microarchitecture (MICRO), pages 327-336, New York, NY, December 2009. Slides (ppt)
  
• Yanjing Li, Onur Mutlu, and Subhasish Mitra,
  "Operating System Scheduling for Efficient Online Self-Test in Robust Systems"
  Proceedings of the International Conference on Computer-Aided Design (ICCAD), pages 201-208, San Jose, CA, November 2009. Slides (ppt) (pdf)
  
• Can Alkan, Jeffrey M. Kidd, Tomas Marques-Bonet, Gozde Aksay, Francesca Antonacci, Fereydoun Hormozdiari, Jacob O. Kitzman, Carl Baker, Maika Malig, Onur Mutlu, S. Cenk Sahinalp, Richard A. Gibbs, and Evan E. Eichler,
  "Personalized copy number and segmental duplication maps using next-generation sequencing"
  Nature Genetics, August 30, [Epub ahead of print], Vol. 41, No. 10, pages 1061-1067, October 2009.

• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn,
  "Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction using Conditional Branch Prediction Hardware"
  IEEE Transactions on Computers (TC), Vol. 58, No. 9, pages 1153-1170, September 2009.
• Kypros Constantinides, Onur Mutlu, Todd Austin, and Valeria Bertacco,
  "A Flexible Software-Based Framework for Online Detection of Hardware Defects"
  IEEE Transactions on Computers (TC), Vol. 58, No. 8, pages 1063-1079, August 2009.
• Thomas Moscibroda and Onur Mutlu,
  "A Case for Bufferless Routing in On-Chip Networks"
  Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 196-207, Austin, TX, June 2009. Slides (pptx)
  
• Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger,
  "Architecting Phase Change Memory as a Scalable DRAM Alternative"
  Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 2-13, Austin, TX, June 2009. Slides (pdf)
  One of the 13 computer architecture papers of 2009 selected as Top Picks by IEEE Micro.
  Selected as a CACM Research Highlight.
• José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Flexible Reference Counting-Based Hardware Acceleration for Garbage Collection"
  Proceedings of the 36th International Symposium on Computer Architecture (ISCA), pages 418-428, Austin, TX, June 2009. Slides (ppt) (pdf)
  
• M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt,
  "Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures"
  Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 253-264, Washington, DC, March 2009. Slides (ppt)
  One of the 13 computer architecture papers of 2009 selected as Top Picks by IEEE Micro.
• Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
  "Techniques for Bandwidth-Efficient Prefetching of Linked Data Structures in Hybrid Prefetching Systems"
  Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA), pages 7-17, Raleigh, NC, February 2009. Slides (ppt)
  Best paper session. One of the three papers nominated for the Best Paper Award by the Program Committee.
• Boris Grot, Joel Hestness, Stephen W. Keckler, and Onur Mutlu,
  "Express Cube Topologies for On-Chip Interconnects"
  Proceedings of the 15th International Symposium on High-Performance Computer Architecture (HPCA), pages 163-174, Raleigh, NC, February 2009. Slides (ppt)
  
• Onur Mutlu and Thomas Moscibroda,
  "Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Memory Controllers"
  IEEE Micro, Special Issue: Micro's Top Picks from 2008 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 29, No. 1, pages 22-32, January/February 2009.

2008

• Kypros Constantinides, Onur Mutlu, and Todd Austin,
  "Online Design Bug Detection: RTL Analysis, Flexible Mechanisms, and Evaluation"
  Proceedings of the 41st International Symposium on Microarchitecture (MICRO), pages 282-293, Lake Como, Italy, November 2008. Slides (ppt)
• Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,
  "Prefetch-Aware DRAM Controllers"
  Proceedings of the 41st International Symposium on Microarchitecture (MICRO), pages 200-209, Lake Como, Italy, November 2008. Slides (ppt)
  An extended version as HPS Technical Report, TR-HPS-2008-002, University of Texas at Austin, September 2008.
• Thomas Moscibroda and Onur Mutlu,
  "Distributed Order Scheduling and its Application to Multi-Core DRAM Controllers"
  Proceedings of the 27th Symposium on Principles of Distributed Computing (PODC), pages 365-374, Toronto, ON, Canada, August 2008. Slides (pptx)
  Best Presentation Award.
• Onur Mutlu and Thomas Moscibroda,
  "Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems"
  Proceedings of the 35th International Symposium on Computer Architecture (ISCA), pages 63-74, Beijing, China, June 2008. Slides (ppt)
  One of the 12 computer architecture papers of 2008 selected as Top Picks by IEEE Micro.
• Engin Ipek, Onur Mutlu, José F. Martínez, and Rich Caruana,
  "Self Optimizing Memory Controllers: A Reinforcement Learning Approach"
  Proceedings of the 35th International Symposium on Computer Architecture (ISCA), pages 39-50, Beijing, China, June 2008. Slides (pptx)
• Sangyeun Cho, Tao Li, and Onur Mutlu,
  "Interaction of Many-core Computer Architecture and Operating Systems: Guest Editors' Introduction"
  IEEE Micro Special Issue (IEEE MICRO), Vol. 28, No. 3, pages 2-5, May/June 2008.
• José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, and Yale N. Patt,
  "Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps"
  Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 80-90, Seattle, WA, March 2008. Slides (ppt) (pdf)
• Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
  "Performance-Aware Speculation Control using Wrong Path Usefulness Prediction"
  Proceedings of the 14th International Symposium on High-Performance Computer Architecture (HPCA), pages 39-49, Salt Lake City, UT, February 2008. Slides (ppt)

2007

• Onur Mutlu and Thomas Moscibroda,
  "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors"
  Proceedings of the 40th International Symposium on Microarchitecture (MICRO), pages 146-158, Chicago, IL, December 2007. Slides (ppt)
• Kypros Constantinides, Onur Mutlu, Todd Austin, and Valeria Bertacco,
  "Software-Based Online Detection of Hardware Defects: Mechanisms, Architectural Support, and Evaluation"
  Proceedings of the 40th International Symposium on Microarchitecture (MICRO), pages 97-108, Chicago, IL, December 2007. Slides (ppt)
• Thomas Moscibroda and Onur Mutlu,
  "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
  Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), pages 257-274, Boston, MA, August 2007. Slides (ppt)
• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn,
  "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization"
  Proceedings of the 34th International Symposium on Computer Architecture (ISCA), pages 424-435, San Diego, CA, June 2007. Slides (ppt)
  An extended version including evaluation of object-oriented Java applications, as HPS Technical Report, TR-HPS-2007-002, University of Texas at Austin, March 2007.
• José A. Joao, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Dynamic Predication of Indirect Jumps"
  IEEE Computer Architecture Letters (CAL), Vol. 6(2), pages 25-28, May 2007.
• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors"
  Proceedings of the 5th International Symposium on Code Generation and Optimization (CGO), pages 367-378, San Jose, CA, March 2007. Slides (ppt) (pdf)
• Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers"
  Proceedings of the 13th International Symposium on High-Performance Computer Architecture (HPCA), pages 63-74, Phoenix, AZ, February 2007. Slides (ppt)
  One of the five papers nominated for the Best Paper Award by the Program Committee.
• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication"
  IEEE Micro, Special Issue: Micro's Top Picks from 2006 Computer Architecture Conferences (MICRO TOP PICKS), Vol. 27, No. 1, pages 94-104, January/February 2007.

2006

• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths"
  Proceedings of the 39th International Symposium on Microarchitecture (MICRO), pages 53-64, Orlando, FL, December 2006. Slides (ppt)
  One of the 11 computer architecture papers of 2006 selected as Top Picks by IEEE Micro.
  Nominated for the Best Paper Award.
  An extended version as HPS Technical Report, TR-HPS-2006-008, University of Texas at Austin, September 2006.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses"
  IEEE Transactions on Computers (TC), Vol. 55, No. 12, pages 1491-1508, December 2006.
• Onur Mutlu,
  "Efficient Runahead Execution Processors"
  Ph.D. Dissertation, HPS Technical Report, TR-HPS-2006-007, July 2006. Slides (ppt)
  Nominated for the ACM Doctoral Dissertation Award by the University of Texas at Austin.
• Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt,
  "A Case for MLP-Aware Cache Replacement"
  Proceedings of the 33rd International Symposium on Computer Architecture (ISCA), pages 167-177, Boston, MA, June 2006. Slides (ppt)
• Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
  "2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set"
  Proceedings of the 4th International Symposium on Code Generation and Optimization (CGO), pages 159-169, New York, NY, March 2006. Slides (ppt) Slides (pdf)
  An extended version as HPS Technical Report, TR-HPS-2006-001, University of Texas at Austin, January 2006.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance"
  IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 10-20, January/February 2006. Submitted final version
• Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt,
  "Wish Branches: Enabling Adaptive and Aggressive Predicated Execution"
  IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 26, No. 1, pages 48-58, January/February 2006. Submitted final version

2005

• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors"
  IEEE Transactions on Computers (TC), Vol. 54, No. 12, pages 1556-1571, December 2005.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns"
  Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 233-244, Barcelona, Spain, November 2005. Slides (ppt) Slides (pdf)
  One of the five papers nominated for the Best Paper Award by the Program Committee.
  An extended version as HPS Technical Report, TR-HPS-2006-004, University of Texas at Austin, April 2006.
• Hyesoon Kim, Onur Mutlu, Jared Stark, and Yale N. Patt,
  "Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution"
  Proceedings of the 38th International Symposium on Microarchitecture (MICRO), pages 43-54, Barcelona, Spain, November 2005. Slides (ppt)
  One of the 13 computer architecture papers of 2005 selected as Top Picks by IEEE Micro.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References"
  International Journal of Parallel Programming (IJPP), Vol. 33, No. 5, pages 529-559, October 2005.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Techniques for Efficient Processing in Runahead Execution Engines"
  Proceedings of the 32nd International Symposium on Computer Architecture (ISCA), pages 370-381, Madison, WI, June 2005. Slides (ppt) Slides (pdf)
  One of the 13 computer architecture papers of 2005 selected as Top Picks by IEEE Micro.
• Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt,
  "Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors"
  Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 434-443, Yokohama, Japan, June 2005. Slides (pdf)
• Onur Mutlu, Hyesoon Kim, Jared Stark, and Yale N. Patt,
  "On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor"
  IEEE Computer Architecture Letters (CAL), Vol. 4, January 2005.

2004

• David N. Armstrong, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
  "Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery"
  Proceeedings of the 37th International Symposium on Microarchitecture (MICRO), pages 119-128, Portland, OR, December 2004. Slides (pdf) Slides (ppt)
  An extended version as HPS Technical Report, TR-HPS-2004-002, University of Texas at Austin, June 2004.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance"
  Proceeedings of the 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), pages 2-9, Foz Do Iguacu, PR, Brazil, October 2004. Slides (pdf)
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "Understanding the Effects of Wrong-Path Memory References on Processor Performance"
  Proceedings of the 3rd Workshop on Memory Performance Issues (WMPI), pages 56-64, Munchen, Germany, June 2004. Slides (pdf)
  An extended version as HPS Technical Report, TR-HPS-2005-001, University of Texas at Austin, January 2005.

2003

• Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,
  "Runahead Execution: An Effective Alternative to Large Instruction Windows"
  IEEE Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences (MICRO TOP PICKS), Vol. 23, No. 6, pages 20-25, November/December 2003.
• Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale N. Patt,
  "Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors"
  Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA), pages 129-140, Anaheim, CA, February 2003. Slides (pdf)
  One of the 15 computer architecture papers of 2003 selected as Top Picks by IEEE Micro.

Dissertation

• Onur Mutlu,
  "Efficient Runahead Execution Processors"
  Ph.D. Dissertation, HPS Technical Report, TR-HPS-2006-007, July 2006. Slides (ppt)
  Nominated for the ACM Doctoral Dissertation Award by the University of Texas at Austin.

Significant Technical Reports (Unpublished)

• George Nychis, Chris Fallin, Thomas Moscibroda, Srinivasan Seshan, and Onur Mutlu,
  "Congestion Control for Scalability in Bufferless On-Chip Networks"
  SAFARI Technical Report, TR-SAFARI-2011-003, Carnegie Mellon University, July 2011.
• Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda,
  "Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning"
  SAFARI Technical Report, TR-SAFARI-2011-002, Carnegie Mellon University, June 2011.
• Reetuparna Das, Onur Mutlu, Akhilesh Kumar, and Mani Azimi,
  "Application-to-Core Mapping Policies to Reduce Interference in On-Chip Networks"
  SAFARI Technical Report, TR-SAFARI-2011-001, Carnegie Mellon University, May 2011.
• Veynu Narasiman, Chang Joo Lee, Michael Shebanow, Rustam Miftakhutdinov, Onur Mutlu, and Yale N. Patt,
  "Improving GPU Performance via Large Warps and Two-Level Warp Scheduling"
  HPS Technical Report, TR-HPS-2010-006, December 2010.
• Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Patt,
  "Prefetch-Aware Shared-Resource Management for Multi-Core Systems"
  HPS Technical Report, TR-HPS-2010-005, December 2010.
• Chang Joo Lee, Eiman Ebrahimi, Veynu Narasiman, Onur Mutlu, and Yale N. Patt,
  "DRAM-Aware Last-Level Cache Replacement"
  HPS Technical Report, TR-HPS-2010-007, December 2010.
• Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt,
  "DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems"
  HPS Technical Report, TR-HPS-2010-002, April 2010.

Other Technical Reports (Extended Versions)

• M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, and Yale N. Patt,
  "An Asymmetric Multi-core Architecture for Accelerating Critical Sections"
  HPS Technical Report, TR-HPS-2008-003, September 2008.
• Chang Joo Lee, Onur Mutlu, Veynu Narasiman, and Yale N. Patt,
  "Prefetch-Aware DRAM Controllers"
  HPS Technical Report, TR-HPS-2008-002, September 2008.
• Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, and Robert S. Cohn,
  "VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization"
  HPS Technical Report, TR-HPS-2007-002, March 2007.
• Thomas Moscibroda and Onur Mutlu,
  "Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"
  Microsoft Research Technical Report, MSR-TR-2007-15, February 2007.
• Chang Joo Lee, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
  "A Performance-Aware Speculation Control Technique Using Wrong Path Usefulness Prediction"
  HPS Technical Report, TR-HPS-2006-010, December 2006.
• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths"
  HPS Technical Report, TR-HPS-2006-008, September 2006.
• Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers"
  HPS Technical Report, TR-HPS-2006-006, May 2006.
• Hyesoon Kim, José A. Joao, Onur Mutlu, and Yale N. Patt,
  "Compiler-Assisted Dynamic Predicated Execution of Complex Control-Flow Structures"
  HPS Technical Report, TR-HPS-2006-005, April 2006.
• Onur Mutlu, Hyesoon Kim, and Yale N. Patt,
  "Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses"
  HPS Technical Report, TR-HPS-2006-004, April 2006.
• Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt,
  "A Case for MLP-Aware Cache Replacement"
  HPS Technical Report, TR-HPS-2006-003, University of Texas at Austin, February 2006.
• Hyesoon Kim, M. Aater Suleman, Onur Mutlu, and Yale N. Patt,
  "2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set"
  HPS Technical Report, TR-HPS-2006-001, University of Texas at Austin, January 2006.
• Hyesoon Kim, Onur Mutlu, Jared Stark, David N. Armstrong, and Yale N. Patt,
  "Wish Branch: A New Control Flow Instruction Combining Conditional Branching and Predicated Execution"
  HPS Technical Report, TR-HPS-2005-002, University of Texas at Austin, February 2005.
• Onur Mutlu, Hyesoon Kim, David N. Armstrong, and Yale N. Patt,
  "An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors"
  HPS Technical Report, TR-HPS-2005-001, University of Texas at Austin, January 2005.
• Moinuddin K. Qureshi, Onur Mutlu, and Yale N. Patt,
  "Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors"
  HPS Technical Report, TR-HPS-2004-004, University of Texas at Austin, December 2004.
• David N. Armstrong, Hyesoon Kim, Onur Mutlu, and Yale N. Patt,
  "Wrong Path Events: Exploiting Illegal and Unusual Program Behavior for Early Misprediction Recovery"
  HPS Technical Report, TR-HPS-2004-002, University of Texas at Austin, June 2004.

Project Reports

• Hyesoon Kim, Onur Mutlu, and Santhosh Srinath,
  "The Design of a 7-stage Pipelined 143 MHz Microprocessor Implementing a Subset of the x86 ISA"
  EE 382N (Microarchitecture) Project Report, University of Texas at Austin, May 2002.
• Onur Mutlu,
  "An Overview of Image Watermarking Algorithms"
  EE 371R (Digital Image and Video Processing) Project Report, University of Texas at Austin, December 2001.
• Onur Mutlu and Chandresh Jain,
  "Effectiveness of TCP for Video Transport"
  CS 384V (Multimedia Systems) Project Report, University of Texas at Austin, November 2001.
• Onur Mutlu and Aditya Bhattacharya,
  "Alpha 21264 Microarchitecture"
  EE 382N (Superscalar Microprocessor Architecture) Slides, University of Texas at Austin, November 2001.
• Chandresh Jain and Onur Mutlu,
  "Design of a Buffer Management Scheme for Video Servers"
  CS 384V (Multimedia Systems) Project Report, University of Texas at Austin, October 2001.
• Onur Mutlu,
  "Memory Dependence Prediction and Access Ordering for Memory Disambiguation and Renaming"
  EE 382N (Superscalar Microprocessor Architecture) Literature Survey, University of Texas at Austin, October 2001.
• Yousuf Ahmed, Chandresh Jain, and Onur Mutlu,
  "A Global Predicate Detector for Distributed Computation"
  EE 382N (Distributed Systems) Project Report, Winner of Best Project Award, University of Texas at Austin, December 2000.
• Onur Mutlu,
  "Effects of the Type of Loud Background Music on Speed of Processing"
  PSYCH 341 (Cognitive Psychology Laboratory) Project Report, University of Michigan, Ann Arbor, August 2000.
• Nai Ka Chung, Tufan C. Karalar, Pak Hei M. Leung, Onur Mutlu, and Cheongyuen Tsang,
  "A Low-Power Low-Cost 16-Bit RISC Microcontroller for Security Systems"
  EECS 427 (VLSI Design) Project Report, University of Michigan, Ann Arbor, April 2000. Chip Image
• Onur Mutlu,
  "A Grammatical Sketch of Even"
  LING 112 (Languages of the World) Project Report, University of Michigan, Ann Arbor, December 1999.