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Scalable Memory Systems (HiPEAC ACACES Summer School 2013)

This is the webpage that hosts preliminary materials for the Scalable Many-Core Memory Systems course to be taught at HiPEAC ACACES Summer School during July 15-19, 2013.

Course Abstract

Link to course abstract at HiPEAC page

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent trends towards increasingly more cores on die, consolidation of diverse workloads on a single chip, and difficulty of DRAM scaling impose new requirements and exacerbate old demands on the memory system. In particular, the need for memory bandwidth and capacity is increasing, applications' interference in memory system increasingly limits system performance and makes the system hard to control, memory energy and power are key design concerns, and DRAM technology consumes significant amounts of energy and does not scale down easily to smaller technology nodes. Fortunately, some promising solution directions exist. In this short course, we will first briefly cover basics of memory systems and examine fundamental tradeoffs. Next, we will describe recent technology, application, and architecture trends and how they change the way we should think of and design memory systems. Finally, we will examine new memory system designs for multi-core architectures to address these trends and requirements. In particular, we will cover recent research on tackling challenges related to scaling the capacity, energy-efficiency, bandwidth, latency, and feature size of main memory. We will potentially examine three major solution directions: 1) how to design more efficient and higher-bandwidth DRAM architectures, 2) how to employ emerging memory technologies in a hybrid memory system, and 3) how to enable more predictable and QoS-aware memory systems.

Overview Reading

The reading below is strongly recommended for attendees of the course. Lectures will revolve around the topics outlined in this 5-page paper. I also encourage you to go through the slides associated with this paper.

Preliminary Slides

The following are the tentative set of slides we will cover in this course. Note that not all slides will be covered.

The slides include links and references to readings and videos associated with each topic.

We will cover three major topics:

We will likely not cover the following two major topics, but the below slides are provided for your benefit. These would likely be useful in putting everything into the entire system perspective.

Final Slides and Videos

The following are the slides covered in each lecture.

Links to Background Lecture Videos

You may find the following lecture videos useful as background information: The following lecture videos can also be useful if you would like to study the optional topics: Finally, if you wish, you can study the entire set of videos that cover a wide range of topics in computer architecture:

Extended Reading List

Most of the readings we will touch on are provided in the preliminary slides above. You can find most readings here.

As time permits, other covered or mentioned readings will be provided on this page as well.

Readings for Topic 1 (DRAM Basics and DRAM Scaling)

Readings for Topic 2 (Emerging Technologies and Hybrid Memories)

Readings for Topic 3 (Memory Interference and QoS-Aware Memory Systems)