18-447 Course Schedule, Spring 2017 (**Not Most Recent**)
Reading assignments are to be completed BEFORE coming to class. (P&H=The Hardware/Software Interface, Fifth Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier. RISCV=The RISC-V Instruction Set Manual, Volume I) You may also find it helpful to preview lecture notes from Spring 2016 before class. There will be additional assigned readings from research papers.
- Part 1: L1~L12 Microrocessors
- Part 2: L13~L19 Memory and I/O
- Part 3: L20~L27 Parallel
(Go to the Course Home Page)
(Go to Blackboard)
| Week | Date | L# | Topic | Readings | Lab Week |
|---|---|---|---|---|---|
| 1 | 1/16 | No classes (Martin Luther King, Jr. Day) | No lab meeting this week |
||
| 1/18 | L1 | Introduction | P&H Ch1 | ||
| 2 | 1/23 | L2 | RISC-V RV32I ISA | P&H Ch2, RISCV Ch1/2/20 | Lab 1A/B start |
| 1/25 | L3 | Single-Cycle Implementation | P&H 4.1~4.4 | ||
| 3 | 1/30 | L4 | ISA Design | P&H Ch2 | Lab 1A due |
| 2/1 | L5 | Performance | P&H Ch1.6, 1.7 and 1.9 | ||
| 4 | 2/6 | L6 | Multi-Cycle Implementations | P&H Appendix D | Lab 1B due |
| 2/8 | L7 | Pipelining: Basics | P&H Ch4.5~4.6 | ||
| 5 | 2/13 | L8 | Pipelining: Data Hazard and Resolution | P&H Ch4.7 | Lab 2 start |
| 2/15 | L9 | Pipelining: Control Hazard and Resolution | P&H Ch4.8 | ||
| 6 | 2/20 | L10 | Pipelining: Branch Prediction | P&H Ch 4.8 | mid-Lab 2 check-off |
| 2/22 | L11 | Pipelining: Exceptions | P&H Ch4.9 and rest | ||
| 7 | 2/27 | Midterm 1 in Class | Lab 2 due | ||
| 3/1 | L12 | Power and Energy | |||
| 8 | 3/6 | L13 | Busses and I/O | Lab 3 start | |
| 3/8 | L14 | Memory Technology and Organization | P&H Ch5.1, 5.2 and 5.5 | ||
| 3/13 | No classes (Spring Break) | ||||
| 3/15 | No classes (Spring Break) | ||||
| 9 | 3/20 | L15 | Caches | P&H Ch5.3,5.4 | |
| 3/22 | L16 | More caches | P&H Ch5.3~5.4 | ||
| 10 | 3/27 | L17 | VM: protection and paging | P&H Ch5.7~5.8 | Lab 3 due |
| 3/29 | L18 | VM: page tables and TLB | P&H Ch5.7~5.8 | ||
| 11 | 4/3 | L19 | VM: modern systems | Rest of Ch5 and paper | Lab 4 start |
| 4/5 | L20 | ILP to Multicores | |||
| 12 | 4/10 | Midterm 2 in class | Lab 4 status check | ||
| 4/12 | L21 | Parallel Computer Architecture | P&H Ch6 | ||
| 13 | 4/17 | L22 | Multithreaded Programming | Lab on Tuesday only |
|
| 4/19 | L23 | Parallel Performance | |||
| 4/20-22 | Spring Carnival | ||||
| 14 | 4/24 | L24 | Cache Coherence | ||
| 4/26 | L25 | Synchronization | |||
| 15 | 5/1 | L26 | Interconnects | Lab 4 due | |
| 5/3 | L27 | Hardware Acceleration | |||
| TBD | Final Exam |
