18-447 Course Schedule, Spring 2011 (**Not Most Recent**)
Reading assignments are to be completed BEFORE coming to class. (P&H=The Hardware/Software Interface, Fourth Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it helpful to preview lecture notes from Spring 2010 before class. There will be additional assigned readings from research papers.
- Part 1: L1~L12 Microrocessors
- Part 2: L13~L19 Memory and I/O
- Part 3: L20~L27 Multiprocessors
(Go to the Course Home Page)
(Go to Blackboard)
| Week | Date | L# | Topic | Readings | Weekly Lab | HW |
|---|---|---|---|---|---|---|
| 1 | 1/10 | L1 | Introduction | P&H Ch1 | No lab meeting this week | |
| 1/12 | L2 | ISA Design | P&H Ch2 (Optional P&H Appendix E.) | |||
| 2 | 1/17 | No classes (Martin Luther King, Jr. Day) | Lab 0: warm-up | HW1 out | ||
| 1/19 | L3 | MIPS ISA | P&H Ch2 | |||
| 3 | 1/24 | L4 | Single-Cycle Implementation | P&H 4.1~4.4 | Lab 1: single-cycle | |
| 1/26 | L5 | Performance and Cost | P&H Ch1.5 and 1.7 | |||
| 4 | 1/31 | L6 | Multi-Cycle Implementations | P&H Appendix D | Lab 1 due | |
| 2/2 | L7 | Pipelining: Basics | P&H Ch4.5~4.6 | HW1 due HW2 out |
||
| 5 | 2/7 | L8 | Pipelining: Data Hazard and Resolution | P&H Ch4.7 | Lab 2: pipelining | |
| 2/9 | L9 | Pipelining: Control Hazard and Resolution | P&H Ch4.8 | |||
| 6 | 2/14 | L10 | Pipelining: Branch Prediction | P&H Ch 4.8 | Lab 2 due | |
| 2/16 | L11 | Pipelining: Exceptions | P&H Ch4.9 | HW2 due | ||
| 7 | 2/21 | L12 | Busses and I/O | P&H Ch6 | Lab 3: control flow | |
| 2/23 | Midterm 1 in Class | |||||
| 8 | 2/28 | L13 | Memory Technology and Organization | P&H Ch5.1 | Lab 3 due | |
| 3/2 | L14 | Caches | P&H Ch5.2~5.3 | |||
| 3/7 | No classes (Spring Break) | |||||
| 3/9 | No classes (Spring Break) | |||||
| 9 | 3/14 | L15 | More caches | P&H Ch5.2~5.3 | No lab meeting this week | HW3 out |
| 3/16 | L16 | Advanced Topic: Automatic Pipelining | Rest of P&H Ch4 | |||
| 10 | 3/21 | L17 | VM: protection and paging | P&H Ch5.4~5.6 | Lab 4: exceptions | |
| 3/23 | L18 | VM: page tables and TLB | Rest of P&H Ch5 | |||
| 11 | 3/28 | L19 | VM: modern systems | assigned paper | Lab 4 due | |
| 3/30 | L20 | ILP to Multicores | P&H Ch7 | HW3 due | ||
| 12 | 4/4 | Midterm 2 in class | Lab 5: Cache & TLB Lab 5 ckp0 due | |||
| 4/6 | L21 | Parallel Computer Architecture | P&H Ch7 | |||
| 13 | 4/11 | L22 | Multithreaded Programming | |||
| 4/13 | L23 | Parallel Performance | ||||
| 4/14-16 | Spring Carnival | |||||
| 14 | 4/18 | L24 | Cache Coherence | Lab 5 ckp1&2 due | HW4 out | |
| 4/20 | L25 | Synchronization | ||||
| 15 | 4/25 | L26 | Interconnects | Lab 5 ckp3 due | ||
| 4/27 | L27 | Advanced Topic: Hybrid Architecture | (Optional P&H Appendix A) | HW4 due | ||
| 5/3 | Final Exam, 1:00pm‐4:00pm, GHC 4307 |
