18-447 Introduction to Computer Architecture, Spring 2018

Special announcement about S15 archive

Due to the new ECE website rollout, some links are misbehaving. You can find 18-447 Spring 2015 archive here until a permanent fix is determined.

Announcements

  • I highly recommend that you review RTL Verilog at HDLBits before start of term.
  • Lab sections will not meet the first week of school.
  • TAs will be available during scheduled lab hours. It does not matter which lab section you sign up for. You are only required to be present for lab check-offs. The entire group must be present for check-off.

Course Description

Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance and cost goals. This course introduces the basic principles and hardware structures of a modern programmable computer. We will learn, for example, how to design the control and datapath for a pipelined RISC processor and how to design fast memory and storage systems. The principles presented in lecture are reinforced in the laboratory through design and simulation of a register transfer (RT) implementation of a RISC processor pipeline in Verilog.

Prerequisites: 18-240 and 15/18-213 and (18340 or 18341 or 18348 or 18349 or 18320)

Staff

  • Instructors
  • Teaching Assistants
    • Daniel Stiffler
    • Ford Seidel
    • Akshit Sharma
    • Sumanth Sridhar

Contact and Office Hours

Please see Canvas.

Meetings

  • Lecture: MW, 12:30PM to 02:20PM, PHA18A
  • Lab Section A: Tue, 10:30AM to 01:20PM, HH1305
  • Lab Section B: Thu, 1:30PM to 04:20PM, HH1305
    Note: It doesn't matter which section you sign up for. You can get checked off during either section period.

Textbooks

  • Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 1st Edition by Patterson and Hennessy, Morgan Kaufmann. (Required)
  • Also useful, textbooks from 18-240 and 15/18-213