18-447 Course Schedule, Spring 2018 (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class. (New for S18: P&H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 1st Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it helpful to preview lecture notes from Spring 2017 before class. There will be additional assigned readings from research papers.

(Go to the Course Home Page)

(Go to Canvas)


Week Date L# Topic Readings Lab Week
1 1/15 No classes (Martin Luther King, Jr. Day) No lab meeting
this week
1/17 L1 Introduction P&H Ch1
2 1/22 L2 RISC-V RV32I ISA P&H Ch2 Lab 1A/B start
1/24 L3 Single-Cycle Implementation P&H 4.1~4.4
3 1/29 L4 ISA Design P&H Ch2 Lab 1A due
1/31 L5 Performance P&H Ch1.6~1.9
4 2/5 L6 Multi-Cycle Implementations P&H Appendix D Lab 1B due
2/7 L7 Pipelining: Basics P&H Ch4.5~4.6
5 2/12 L8 Pipelining: Data Hazard and Resolution P&H Ch4.7 Lab 2 start
2/14 L9 Pipelining: Control Hazard and Resolution P&H Ch4.8
6 2/19 L10 Pipelining: Branch Prediction P&H Ch4.8 mid-Lab 2 check-off
2/21 L11 Pipelining: Exceptions P&H Ch4.9 and rest
7 2/26 Midterm 1 in Class Lab 2 due
2/28 L12 Power and Energy
8 3/5 L13 Busses and I/O Ch5.5 Lab 3 start
3/7 L14 Memory Technology and Organization P&H Ch5.1, 5.2
3/12 No classes (Spring Break)
3/14 No classes (Spring Break)
9 3/19 L15 Caches P&H Ch5.3
3/21 L16 More caches P&H Ch5.4, 5.9
10 3/26 L17 VM: protection and paging P&H Ch5.6~5.8 Lab 3 due
3/28 L18 VM: page tables and TLB P&H Ch5.6~5.8
11 4/2 L19 VM: modern systems Rest of Ch5 and paper Lab 4 start
4/4 L20 ILP to multicore
12 4/9 Midterm 2 in class Lab 4 status check
4/11 L21 Parallel Computer Architecture P&H Ch6
13 4/16 L22 Multithreaded Programming Lab on
Tuesday only
4/18 L23 Parallel Performance Ch5.15
4/19-21 Spring Carnival
14 4/23 L24 Cache Coherence Ch5.10
4/25 L25 Synchronization Ch2.11, 5.14
15 4/30 L26 Interconnects Lab 4 due
5/2 L27 Hardware Acceleration
5/10 Final Exam, 1pm~4pm