Table of Contents

18-643 Course Schedule, Fall 2016 (**Not Most Recent**)

  • Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2015 before class.
  • Reading assignments are to be completed BEFORE coming to class.
    • RC=Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation by Scott Hauck and Andre DeHon.
    • ZB=The Zynq Book by Louise H. Crockett, et al.
    • Additional papers
    • “skim” are recommended supplemental materials. You should read them with as much interest as you have. Read enough to know what is all covered so you can come back to a reading if you develop more interest later.
  • There are 4 two-week-long do-at-home labs in the first half of the semester. There is a single project for the second half of the semester.
  • Please note the attendance-mandatory dates for the midterm and in-class project presentations. Audience of overflow presentations on Wednesdays (if necessary) is not required.
  • Go to the Course Home Page
  • Go to Blackboard
  • Go to Piazza


Schedule and Lecture Notes

Week Date L# Topic Readings Lab
1 8/30 L1 Introduction 1st-Half Kick Off: [Trimberger15] Lab 0: Warm-Up
9/1 L2 FPGA Basics RC Ch 1
(skim RC Ch 13,14)
2 9/6 L3 FPGA Less Basic (skim [Ahmed16])
9/8 L4 SoC FPGAs ZB Ch 2
(skim ZB Ch 3,10)]
3 9/13 L5 Design Metrics read H&P chapter on performance if you haven't
read for later [Kung86][Shao14]		 Lab 1: Vivado SoC
9/15 L6 Hard vs Soft Logic (skim [Kuon06][Chung10][Papamichael12])
4 9/20 L7 Structural RTL HDL Compiler for Verilog Reference Manual
Vivado Design Suite User Guide: Synthesis (UG901)
9/22 L8 Abstract Models (skim RC Ch5,8,9,10)
5 9/27 L9 C-to-HW [Edwards05] (skim IEEE Design & Test of Computers Issue 4, July-Aug. 2009
RC Ch7, ZB Ch 14) 		Lab 2: Vivado HLS
9/29 L10 Vivado HLS ZB Ch 15
Vivado Design Suite User Guide: High-Level Synthesis (UG902)
6 10/4 L11 Altera OpenCL RC Ch 10
(skim Altera SDK for OpenCL: Programming Guide)
10/6 L12 Domain-Specific HLS (skim [Milder12] Spiral DFTgen)
7 10/11 L13 FPGA Memory Architecture Lab 3: HW Accelerate
10/13 L14 CoRAM FPGA Computing Abstraction [Chung11][Weisz15]
8 10/18 Midterm 1 2nd-Half Kick Off: [Tessier15] (skim [DeHon15])
10/20 L15 Partial Reconfiguration
Guest Lecturer: Marie Nguyen
9 10/25 Term Project Proposal Student Presentations
10/26 Term Project Proposal Student Presentations (overflow if necessary)
10/27 Term Project Proposal Student Presentations
10 11/1 L16 Convey and Maxeler Review [Brewer10] or [Pell13]
11/3 L17 FPGAs in Datacenter (Catapult)
Guest Lecturer: Derek Chiou (MSR) 		Review [Putnam14] or [Caulfield16]
11 11/8 L18 Cache Coherent FPGAs (IBM CAPI, Intel QPI) Review [Oliver11] or [Stuecheli15]
11/10 L19 Coarse-Grained Reconfigurable Array (TRIPS, RAW) Review [Taylor02] or [Burger04] (skim [Hartenstein01] )
12 11/15 L20 High-Level Synthesis Review [Choi16] or [Goeders14]
11/17 L21 Applications Review [Ham16] or [Hegarty16]
13 11/22 L22 Platform and Programming Abstractions
Guest Lecturer: Kermin Fleming (Intel) 		Review (as part of Week 12 options) [Fleming14] ( LEAP FPGA OS)) or [Kirchgessner12] (VirtualRC)
11/24 Thanksgiving
14 11/29 L23 Applications Review [Hegde16] or [Zhang15]
12/1 L24 Applications Review [Shaw07] or [Wang15]
15 12/6 Term Project Student Presentations
12/7 Term Project Student Presentations (overflow if necessary)
12/8 Term Project Student Presentations


References

All of the following references can be found online. Please respect copyrights. CMU students have access to IEEE Xplore and ACM Digital Library from CMU network.

  • [Ahmed16] S. Ahmed, et al., “A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform,” IEEE Micro, March-April 2016.
  • [Brewer10] T. M. Brewer, “Instruction Set Innovations for the Convey HC-1 Computer,” IEEE Micro, March-April 2010.
  • [Burger04] D. Burger, et al., “Scaling to the end of silicon with EDGE architectures,” IEEE Computer, July 2004.
  • [Caufield16] A. Caulfield, et al., “A Cloud-Scale Acceleration Architecture,” MICRO, October 2016.
  • [Choi16] J. Choi, et al., “A Unified Software Approach to Specify Pipeline and Spatial Parallelism in FPGA Hardware,” Proceedings of ASAP, 2016.
  • [Chung10] E. S. Chung, et al., “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?” MICRO, 2010.
  • [Chung11] E. S. Chung, et al., “CoRAM: an In-Fabric Memory Architecture for FPGA-Based Computing,” ISFPGA 2011.
  • [DeHon15] A. DeHon, “Fundamental Underpinnings of Reconfigurable Computing Architectures,” Proceedings of the IEEE, March 2015.
  • [Edwards05] S. A. Edwards, “The challenges of hardware synthesis from C-like languages,” Proceedings of DATE, 2005.
  • [Fleming14] K. Fleming, et al., “The LEAP FPGA Operating System,” FPL, 2014.
  • [Goeders14] J. Goeders, et al., “Effective FPGA debug for high-level synthesis generated circuits,” Proceedings of FPL, 2014.
  • [Ham16] T. J. Ham, et al., “Graphicionado: A High-Performance and Energy Efficient Accelerator for Graph Analytics,” MICRO 2016.
  • [Hartenstein01] R. Hartenstein, “Coarse Grain Reconfigurable Architecture,” ASPDAC, 2001.
  • [Hegarty16] J. Hegarty, et al., “Rigel: flexible multi-rate image processing hardware,” Proceedings of SIGGRAPH, 2016.
  • [Hegde16] G Hegde, et al., “CaffePresso: An Optimized Library for Deep Learning on Embedded Accelerator-based platforms,” CODES+ISSS, 2016.
  • [Kirchgessner12] R. Kirchgessner, et al., “VirtualRC: a Virtual FPGA Platform for Applications and Tools Portability,” ISFPGA, 2012.
  • [Kuon06] I. Kuon and J. Rose, “Measuring the Gap between FPGAs and ASICs,” ISFPGA, 2006.
  • [Kung86] H. T. Kung, “Memory Requirements for Balanced Computer Architectures,” ISCA 1986.
  • [Milder12] P. Milder, et al., “Computer Generation of Hardware for Linear Digital Signal Processing Transforms,” ACM TODAES, April 2012.
  • [Oliver11] N. Oliver, et al., “A Reconfigurable Computing System Based on a Cache-Coherent Fabric,” ReConFig, 2011.
  • [Papamichael12] M. Papamichael, et al., “CONNECT: Re-Examining Conventional Wisdom for Designing NOCS in the Context of FPGAs,” ISFPGA, 2012.
  • [Pell13] O. Pell, et al., “Maximum Performance Computing with Dataflow Engines,” in High-Performance Computing Using FPGAs, Springer, 2013.
  • [Putnam14] A. Putnam, et al., “A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services,” ISCA, 2014.
  • [Shao14] Y.S.Shao, et al., “Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures,” ISCA, 2014.
  • [Shaw07] D.E. Shaw, et al., “Anton, a special-purpose machine for molecular dynamics simulation,” Proceedings of ISCA, 2007.
  • [Stuecheli15] J. Stuecheli, et al., “CAPI: A Coherent Accelerator Processor Interface,” IBM Journal of Research and Development , Jan.-Feb. 2015.
  • [Taylor02 M. B. Taylor, et al., “The Raw microprocessor: a computational fabric for software circuits and general-purpose programs,” IEEE Micro, 2002.
  • [Tessier15] R. Tessier, et al., “Reconfigurable Computing Architectures,” Proceedings of the IEEE, March 2015.
  • [Trimberger15] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015.
  • [Wang15] K. Wang, et al., “Association Rule Mining with the Micron Automata Processor,” Proceedings of IPDPS, 2015.
  • [Weisz15] G. Weisz, et al., “CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing,” Proceedings of FPL, 2015.
  • [Zhang15] C. Zhang, et al., “Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks,” Proceedings of FPGA, 2015.