18-643 Reconfigurable Logic: Technology, Architecture and Applications

18-643 is on hiatus for Fall 2024. Good alternatives I would take instead are

• 18740 Modern Computer Architecture and Design
• 18645 How to Write Fast Code I
• 18640 Hardware Arithmetic for Machine Learning
• 15618 Parallel Computer Architecture and Programming

You are welcome to try the 18-643 Labs (need access to CMU Google Drive).

• What this course is about (Youtube)
• When the course started in 2015, “RTL” was made a required background. If you are skilled in high-performance parallel programming, you should do fine in the current course. (If you need an RTL refresher, go to HDLBits).
• Recitation attendance is optional. Recitation provides supplemental help on labs and projects. We are likely to reschedule the time by a popularity vote come fall.
• No recitation first two weeks of school
• After the semester starts, students on waitlist should email the instructor to get temporary access to Canvas.

• Fall 2023 Lecture Schedule and Notes
• Preview lecture notes from the last completed semester
• Communications
  • visit Canvas for official announcements, handouts, work submissions, etc.
  • use Piazza for lab-related discussions
  • subscribe seminars@nexusfpga.org to receive FPGA related seminars announcements (available to anyone with cmu.edu or pitt.edu address)
• Academic Services Center

Three decades since their original inception as a lower-cost compromise to ASICs, modern Field Programmable Gate Arrays (FPGAs) are versatile and powerful systems-on-a-chip for many applications that need both hardware level efficiency and the flexibility of reprogrammability. More recently, FPGAs have also emerged as a formidable computing substrate with applications ranging from data centers to mobile devices. This course offers a comprehensive coverage of modern FPGAs in terms of technology, architecture and applications. The coverage will also extend into on-going research investigations of future directions. Students will take part in a substantial design project applying the latest FPGA platforms to compute acceleration. Register-Transfer Level (RTL) hardware design experience is required.

Prerequisites: 18-341 or 18-447

• Instructor
  • James C. Hoe (contact)
• Teaching Assistants
  • Chengyue Wang
  • Jiajun Hu
  • See Canvas for contact info and office hours
• Academic Services Center

• Lectures: Monday and Wednesday, 12:00pm to 1:50pm, SH234
• Recitations: TBD.

• None required. Please see Canvas for supplemental reference materials.

• Intel/VMware Crossroads 3D-FPGA Academic Research Center
• Computer Architecture Lab at Carnegie Mellon (CALCM)
• HDLBits Verilog Practice
• A Short Intro to ModelSim Verilog Simulator