Table of Contents

18-643 Course Schedule, Fall 2015 (**Not Most Recent**)

  • Lecture notes are posted within 24 hours after the lecture
  • Reading assignments are to be completed BEFORE coming to class.
    • RC=Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation by Scott Hauck and Andre DeHon.
    • ZB=The Zynq Book by Louise H. Crockett, et al.
    • Additional papers
  • There are 4 two-week-long do-at-home labs in the first half of the semester. There is a single project for the second half of the semester.
  • Please note the dates for midterms and required in-class presentations.
  • (Go to the Course Home Page)
  • (Go to Blackboard)


Schedule and Lecture Notes

Week Date L# Topic Readings Lab
1 9/1 L1 Introductions (skim [Trimberger15]) Lab 0: Warm-Up
9/3 L2 FPGA Basics RC Ch 1
(skim RC Ch 13,14)
2 9/8 L3 FPGA Less Basic (skim [DeHon15])
9/10 L4 SoC FPGAs ZB Ch 2
(skim ZB Ch 3,10)]
3 9/15 L5 Zedboard ZB Ch 6,8 Lab 1: Vivado SoC
9/17 L6 Performance read H&P chapter on performance if you haven't
read for later [Kung86][Shao14]
4 9/22 L7 Hard vs Soft Logic (skim [Kuon06][Chung10][Papamichael12])
9/24 L8 Structural RTL HDL Compiler for Verilog Reference Manual
Vivado Design Suite User Guide: Synthesis (UG901)
5 9/29 L9 Abstract Models (skim RC Ch5,8,9,10) Lab 2: Vivado HLS
10/1 L10 C-to-HW (skim IEEE Design & Test of Computers Issue 4, July-Aug. 2009
RC Ch7, ZB Ch 14)
6 10/6 L11 Vivado HLS ZB Ch 15
Vivado Design Suite User Guide: High-Level Synthesis (UG902)
10/8 L12 Confessions of a User (Marie Nguyen)
7 10/13 L13 Spiral “HLS” (skim [Milder12][Akin12]) Lab 3: HW Accelerate
10/15 Midterm 1
8 10/20 L14 Machine Learning in Data Center (Eric Chung, MSR) [Ovtcharov15]
10/22 L15 Reconfigurable Computing [Tessier15]
10/23 Midsemester Break
9 10/27 Term Project Proposal Student Presentations Project Start
10/29 Term Project Proposal Student Presentations
10 11/3 L16 Convey and Maxeler Review [Brewer10] or [Pell13]
11/5 L17 Cache Coherent FPGAs (IBM CAPI, Intel QPI) Review [Oliver11] or [Stuecheli15]
11 11/10 L18 LEAP FPGA OS (Michael Adler, Intel) Review [Fleming14]
11/12 L19 Programming Abstractions (VirtualRC,CoRAM) Review [Chung11] or [Kirchgessner12]
12 11/17 L20 FPGAs in Datacenter (Catapult) Review [Putnam14]
11/19 L21 Coarse-Grained Reconfigurable Array (TRIPS, RAW) Review [Taylor02] or [Burger04] (skim [Hartenstein01] )
13 11/24 L22 Computing Applications Review one of [Xcell15]
11/26 Thanksgiving
14 12/1 Term Project Student Presentations
12/3 Term Project Student Presentations Project End
15 12/8 L23 slack
12/10 Midterm 2


References

All of the following references can be found online. Please respect copyrights. CMU students have access to IEEE Xplore and ACM Digital Library from CMU network.

  • [Akin12] B. Akin, et al., “Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes,” FCCM, 2012.
  • [Brewer10] T. M. Brewer, “Instruction Set Innovations for the Convey HC-1 Computer,” IEEE Micro, March-April 2010.
  • [Burger04] D. Burger, et al., “Scaling to the end of silicon with EDGE architectures,” IEEE Computer, July 2004.
  • [Chung10] E. S. Chung, et al., “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?” MICRO, 2010.
  • [Chung11] E. S. Chung, et al., “CoRAM: an in-fabric memory architecture for FPGA-based computing,” ISFPGA 2011.
  • [DeHon15] A. DeHon, “Fundamental Underpinnings of Reconfigurable Computing Architectures,” Proceedings of the IEEE, March 2015.
  • [Fleming14] K. Fleming, et al., “The LEAP FPGA operating system,” FPL, 2014.
  • [Hartenstein01] R. Hartenstein, “Coarse grain reconfigurable architecture,” ASPDAC, 2001.
  • [Kirchgessner12] R. Kirchgessner, et al., “VirtualRC: a virtual FPGA platform for applications and tools portability,” ISFPGA, 2012.
  • [Kuon06] I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” ISFPGA, 2006.
  • [Kung86] H. T. Kung, “Memory requirements for balanced computer architectures,” ISCA 1986.
  • [Milder12] P. Milder, et al., “Computer Generation of Hardware for Linear Digital Signal Processing Transforms,” ACM TODAES, April 2012.
  • [Oliver11] N. Oliver, et al., “A Reconfigurable Computing System Based on a Cache-Coherent Fabric,” ReConFig, 2011.
  • [Ovtcharov15] K. Ovtcharov, et al., “Accelerating Deep Convolutional Neural Networks Using Specialized Hardware,” Microsoft Research, 2015.
  • [Papamichael12] M. Papamichael, et al., “CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs,” ISFPGA, 2012.
  • [Pell13] O. Pell, et al., “Maximum Performance Computing with Dataflow Engines,” in High-Performance Computing Using FPGAs, Springer, 2013.
  • [Putnam14] A. Putnam, et al., “A reconfigurable fabric for accelerating large-scale datacenter services,” ISCA, 2014.
  • [Shao14] Y.S.Shao, et al., “Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures,” ISCA, 2014.
  • [Stuecheli15] J. Stuecheli, et al., “CAPI: A Coherent Accelerator Processor Interface,” IBM Journal of Research and Development , Jan.-Feb. 2015.
  • [Taylor02 M. B. Taylor, et al., “The Raw microprocessor: a computational fabric for software circuits and general-purpose programs,” IEEE Micro, 2002.
  • [Tessier15] R. Tessier, et al. “Reconfigurable Computing Architectures,” Proceedings of the IEEE, March 2015.
  • [Trimberger15] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015.
  • [XCell15] XCell Journal, Xilinx, Third Quarter, 2015.