18-643 Course Schedule, Fall 2017 (**Not Most Recent**)
- - Schedule and Lecture Notes
  - References

18-643 Course Schedule, Fall 2017 (Not Most Recent)

Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2016 before class.

Reading assignments are to be completed BEFORE coming to class.
- RC=Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation by Scott Hauck and Andre DeHon.
- ZB=The Zynq Book by Louise H. Crockett, et al.
- Additional papers
- “skim” are recommended supplemental materials. You should read them with as much interest as you have. Read enough to know what is all covered so you can come back to a reading if you develop more interest later.
There are 4 two-week-long do-at-home labs in the first half of the semester. There is a single project for the second half of the semester.
Please note the attendance-mandatory dates for the midterm and in-class project presentations. Audience of overflow presentations on Wednesdays (if necessary) is not required.
Go to the Course Home Page
Go to Blackboard (Important: students on waitlist should email instructor for access to Blackboard)
Go to Piazza

Schedule and Lecture Notes

Week	Date	L#	Topic	Readings	Lab
1	8/29	L1	Introduction	1st-Half Kick Off: [Trimberger15] check out Microsoft Brainwave	Lab 0: Warm-Up
	8/31	L2	FPGA Basics	RC Ch 1 (skim RC Ch 13,14)
2	9/5	L3	FPGA Less Basic	(skim [Ahmed16])
	9/7	L4	Partial Reconfig and SoC	ZB 5.6 and Ch 2 (skim ZB Ch 3,10)]
3	9/12	L5	Design Metrics	read H&P chapter on performance if you haven't read for later [Kung86][Shao14]	Lab 1: Vivado SoC
	9/14	L6	Hard vs Soft Logic	(skim [Kuon06][Chung10][Papamichael12])
4	9/19	L7	Structural RTL	HDL Compiler for Verilog Reference Manual Vivado Design Suite User Guide: Synthesis (UG901)
	9/21	L8	Abstract Models	(skim RC Ch5,8,9,10)
5	9/26	L9	C-to-HW	[Edwards05] (skim IEEE Design & Test of Computers Issue 4, July-Aug. 2009 RC Ch7, ZB Ch 14)	Lab 2: Vivado HLS, read [Zhang15]
	9/28	L10	Vivado HLS	ZB Ch 15 Vivado Design Suite User Guide: High-Level Synthesis (UG902)
6	10/3	L11	Altera OpenCL	RC Ch 10 [Aydonat17] (skim Altera SDK for OpenCL: Programming Guide)
	10/5	L12	Domain-Specific HLS	(skim [Milder12] Spiral DFTgen)
7	10/10	L13	FPGA Memory Architecture		Lab 3: HW Accelerate
	10/12	L14	CoRAM FPGA Computing Abstraction Lecturer: Joe Melber	[Chung11]
8	10/17		Midterm 1	2nd-Half Kick Off: [Tessier15] (skim [DeHon15])
	10/19	L15	Smart Headlights Lecturer: Marie Nguyen
9	10/24		Term Project Proposal Student Presentations
	10/26		Term Project Proposal Student Presentations
10	10/31	L16	Accelerator Landscape	Review [Nurvitadhi16] or [Giefers16]
	11/2	L17	Virtualization and Abstraction	Review [Fleming14] or [Weisz15]
11	11/7	L18	Coarse-Grained Reconfigurable Array and Overlay Architecture	Review [Zain-ul-Abdin09] or [Severance12]
	11/9	L19	FPGAs in Datacenter Guest Lecture: Michael Papamichael (MSR)	Review [Putnam14] or [Caulfield16]
12	11/14	L20	DSL: streaming and graphics	Review [Prabhakar17] or [Hegarty16]
	11/16	L21	FPGA in Algorithmic Trading Guest Lecturer: Todd Strader (Two Sigma)	Review [Li16] or [Wang17]
13	11/21	L22	Irregular Parallelism	Review [Ham16] or [Li17]
	11/23		Thanksgiving
14	11/28	L23	no class meeting
	11/30	L24	Machine Learning	Review [Han17] or [Jouppi17] with week 13
15	12/5		Term Project Student Presentations
	12/7		Term Project Student Presentations

References

All of the following references can be found online. Please respect copyrights. CMU students have access to IEEE Xplore and ACM Digital Library from CMU network.

[Aydonat17] Aydonat, et al., “An OpenCL Deep Learning Accelerator on Arria 10,” Proceedings of ISFPGA, 2017.
[Ahmed16] S. Ahmed, et al., “A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform,” IEEE Micro, March-April 2016.
[Caulfield16] A. Caulfield, et al., “A Cloud-Scale Acceleration Architecture,” Proceedings of MICRO, 2016.
[Chung10] E. S. Chung, et al., “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?” MICRO, 2010.
[Chung11] E. S. Chung, et al., “CoRAM: an In-Fabric Memory Architecture for FPGA-Based Computing,” Proceedings of ISFPGA, 2011.
[DeHon15] A. DeHon, “Fundamental Underpinnings of Reconfigurable Computing Architectures,” Proceedings of the IEEE, March 2015.
[Edwards05] S. A. Edwards, “The challenges of hardware synthesis from C-like languages,” Proceedings of DATE, 2005.
[Fleming14] K. Fleming, et al., “The LEAP FPGA Operating System,” Proceedings of FPL, 2014.
[Giefers16] H. Giefers, et al., “Analyzing the energy-efficiency of sparse matrix multiplication on heterogeneous systems: A comparative study of GPU, Xeon Phi and FPGA,” Proceedings of ISPASS, 2016.
[Ham16] T. J. Ham, et al., “Graphicionado: A High-Performance and Energy Efficient Accelerator for Graph Analytics,” Proceedings of MICRO, 2016.
[Han17] S. Han, et al., “ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA,” Proceedings of ISFPGA, 2017.
[Hegarty16] J. Hegarty, et al., “Rigel: flexible multi-rate image processing hardware,” Proceedings of SIGGRAPH, 2016.
[Jouppi17] N. P. Jouppi, et al., “In-Datacenter Performance Analysis of a Tensor Processing Unit,” Proceedings of ISCA, 2017.
[Kuon06] I. Kuon and J. Rose, “Measuring the Gap between FPGAs and ASICs,” Proceedings of ISFPGA, 2006.
[Kung86] H. T. Kung, “Memory Requirements for Balanced Computer Architectures,” Proceedings of ISCA, 1986.
[Li16] B. Li, et al., “ClickNP: Highly Flexible and High Performance Network Processing with Reconfigurable Hardware,” Proceedings of SIGCOMM, 2016.
[Li17] Z. Li, et al., “Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware,” Proceedings of ISCA, June 2017.
[Milder12] P. Milder, et al., “Computer Generation of Hardware for Linear Digital Signal Processing Transforms,” ACM TODAES, April 2012.
[Nurvitadhi16] E. Nurvitadhi, et al., “Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC,” Proceedings of FPT, 2016.
[Papamichael12] M. Papamichael, et al., “CONNECT: Re-Examining Conventional Wisdom for Designing NOCS in the Context of FPGAs,” Proceedings of ISFPGA, 2012.
[Prabhakar17] R. Prabhakar, et al., “Plasticine: A Reconfigurable Architecture For Parallel Patterns,” Proceedings of ISCA, 2017.
[Putnam14] A. Putnam, et al., “A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services,” Proceedings of ISCA, 2014.
[Severance12] A. Severance, et al., “VENICE: A compact vector processor for FPGA applications,” Proceedings of FPT, 2012.
[Shao14] Y.S. Shao, et al., “Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures,” Proceedings of ISCA, 2014.
[Tessier15] R. Tessier, et al., “Reconfigurable Computing Architectures,” Proceedings of the IEEE, March 2015.
[Trimberger15] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015.
[Wang17] H. Wang, et al., “P4FPGA: A Rapid Prototyping Framework for P4,” Proceedings of SOSR, 2017.
[Weisz15] G. Weisz, et al., “CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing,” Proceedings of FPL, 2015.
[Zain-ul-Abdin09] Zain-ul-Abdin, et al., “Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing,” Microprocessors and Microsystems, Volume 33, Issue 3, May 2009.
[Zhang15] C. Zhang, et al., “Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks,” Proceedings of ISFPGA, 2015.

Table of Contents

18-643 Course Schedule, Fall 2017 (**Not Most Recent**)

Schedule and Lecture Notes

References

18-643 Course Schedule, Fall 2017 (Not Most Recent)