Three-Phase Infeasibility Analysis for Distribution Grid Studies,  Power Systems Computation Conference (PSCC)

E. Foster, A. Pandey, L. Pileggi, Three-Phase Infeasibility Analysis for Distribution Grid Studies,  Power Systems Computation Conference (PSCC), June 27-July 1, 2022.

“Large Scale Multi-Period Optimal Power Flow with Energy Storage Systems Using Differential Dynamic Programming,”

Agarwal, L. Pileggi, “Large Scale Multi-Period Optimal Power Flow with Energy Storage Systems Using Differential Dynamic Programming,” IEEE PES Transactions on Power Systems, 2021.

“Dynamic Graph-Based Anomaly Detection in the Electrical Grid,” IEEE Transactions on Power Systems

(Cindy) Li, A. Pandey, B. Hooi, C. Faloutsos, and L. Pileggi, “Dynamic Graph-Based Anomaly Detection in the Electrical Grid,” IEEE Transactions on Power Systems, doi: 10.1109/TPWRS.2021.31328

Fast AC Steady-State Power Grid Simulation and Optimization Using Prior Knowledge

A. Agarwal, A. Pandey and L. Pileggi, Fast AC Steady-State Power Grid Simulation and Optimization Using Prior Knowledge, (Best Paper Award) IEEE PES General Meeting, July 25-29, 2021.

A WLAV-based Robust Hybrid State Estimation using Circuit-theoretic Approach

S. (Cindy) Li, A. Pandey, and L. Pileggi, A WLAV-based Robust Hybrid State Estimation using Circuit-theoretic Approach, (Best Paper Session) IEEE PES General Meeting, July 25-29, 2021.

Analytical Inverter-Based Distributed Generator Model for Power Flow Analysis

N. T. Bandele, A. Pandey and L. Pileggi, Analytical Inverter-Based Distributed Generator Model for Power Flow Analysis, IEEE PES General Meeting, July 25-29, 2021.

Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows

P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.

Split-Chip Design to prevent IP Reverse Engineering

S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra and L. Pileggi, “Split-Chip Design to prevent IP Reverse Engineering,” in IEEE Design & Test, doi: 10.1109/MDAT.2020.3033255.

Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow

A. Pandey, A. Agarwal, L. Pileggi, “Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow,” Hawaii International Conference on System Sciences-54, Hawaii, 2021.

Top-down physical design of soft embedded FPGA fabrics

P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.