Split-Chip Design to prevent IP Reverse Engineering

/in , , /by

S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra and L. Pileggi, “Split-Chip Design to prevent IP Reverse Engineering,” in IEEE Design & Test, doi: 10.1109/MDAT.2020.3033255.

Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation

/in , , /by

Jovicic, M. Jereminov, L. Pileggi, Gabriela Hug, Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation, IEEE Transactions on Power Systems, February 2020 (10.1109/TPWRS.2020.2974459).

Evaluating Feasibility within Power Flow

/in , , /by

Jereminov, D.M. Bromberg, A. Pandey, M.R. Wagner, and L. Pileggi, “Evaluating Feasibility within Power Flow,” IEEE Transactions on Smart Grid, Vol. 11, No. 4, July 2020. DOI: 10.1109/TSG.2020.2966930.

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

/in , , /by

M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)

Steady-State Simulation for Combined Transmission and Distribution Systems

/in , , /by

A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, Vol 11, Issue 2, March 2020. (DOI: 10.1109/TSG.2019.2932403).

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

/in , , /by

S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography

/in , , , /by

I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).

A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks

/in , , /by

S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.

Robust Power Flow and Three Phase Power Flow Analyses

/in , , /by

A. Pandey, M. Jereminov, M. R. Wagner, D. M. Bromberg, G. Hug, L. Pileggi, Robust Power Flow and Three Phase Power Flow Analyses, IEEE Transactions on Power Systems, Vol. 34, Issue:1, pp. 616-626, January 2019.

Equivalent Circuit Formulation for Solving AC Optimal Power Flow

/in , , /by

M. Jereminov, A. Pandey, L. Pileggi, Equivalent Circuit Formulation for Solving AC Optimal Power Flow, IEEE Transactions on Power Systems, December 2018.