1. Martin Wagner, Equivalent Circuit Formulation based Framework for Probabilistic Power System Analysis, September 6, 2019.
  2. Marko Jereminov, Equivalent Circuit Programming, August 26, 2019.
  3. Mehmet Meric Isgenc, Enabling Design of Low-Volume High-Performance Integrated Circuits, April 9, 2019.
  4. Fazle Sadi, Accelerating Sparse Matrix Kernels with Co-Optimized Architecture, December 17, 2018.
  5. Amritanshu Pandey, Robust Steady-State Power Grid Analysis using Equivalent Circuit Formulation with Circuit Simulation Methods, August 16, 2018.
  6. Thomas Jackson, Building Efficient Neuromorphic Networks in Hardware with Mixed Signal Techniques and Emerging Technologies, December 5, 2017.
  7. Shaolong Liu, SAR ADCs Design and Calibration in Nano-scaled Technologies, September 15, 2017.
  8. Jinling Xu, “Self-healing Narrowband MEMS Filter Design for RF Receivers,” May 2, 2017.
  9. Ekin Sumbul, “A Novel Design Methodology for Synthesizing Logic-in-Memory Blocks,” July 7, 2015.
  10. Renzhi Liu, “Digital Calibration Method for High Resolution in Analog/RF Designs,” June 29, 2015.
  11. Vehbi Calayir, Neurocomputing and Associative Memories Based on Emerging Technologies: Co-optimization of Technology and Architecture,” September 17, 2014.
  12. David Bromberg, “Current-Driven Magnetic Devices for Non-Volatile Logic and Memory,” August 8, 2014.
  13. Kaushik Vaidyanathan, “Exploiting Challenges of Sub-20 nm CMOS for Affordable Technology Scaling,” March 7, 2014.
  14. Hung-Chu (Vanessa) Chen, “Low-Power Giga-Hertz Analog-to-Digital Converters with Background Calibration,” November 25, 2013.
  15. Qiuling (Jolin) Zhu, “Application Specific Logic in Memory,” November 13, 2013.
  16. Cheng-Yuan Wen, “Phase-Change Recongifurable RF and Analog Integrated Circuits,” February 8, 2013.
  17. Daniel Morris, “mLogic: Nonvolatile Pulsed‐Current Logic and Memory Circuits, September 19, 2012.
  18. Soner Yaldiz, “Self-Healing Design Methodologies for Analog Integrated Circuits,” January 6, 2012.
  19. Umut Arslan, “Joint Exploration of Low-Cost Regular Fabrics and Variation-Tolerant Circuit Techniques for Nanoscale SRAM,” October 21, 2010.
  20. Vyacheslav V. Rovner, “Circuit – Layout Co-optimization for Extremely Regular Design Fabrics in Nanoscale ICs,” September 28, 2010.
  21. Gokce Keskin, “Self-Healing Circuits Using Statistical Element Selection,” September 09, 2010.
  22. Alyssa Bonnoit, “Reducing Power using Body Biasing in Microprocessors With Dynamic Voltage/Frequency Scaling,” April 30, 2010.
  23. Jonathan Proesel, “Flash Analog-to-Digital Converter Design Based on Statistical Post-Silicon Calibration,” April 20, 2010.
  24. Jian Wang, “Response Surface Modeling for Analog and Mixed Signal Design,” August 2008.
  25. Kim Yaw Tong, “Design Regularity for Robust Integrated Circuits,” December 6, 2006.
  26. Padmini Gopalakrishnan, “Applications of Metric Embedding to Regular IC Optimization, “ October 2006.
  27. Veerbhan Kheterpal, “Logic Synthesis for Regular Fabrics,” August 2006.
  28. Jiayong (Kelvin) Le, “Variation-Aware Timing Analysis and Optimization for Digital ICs,” July 2006.
  29. Xin Li, “Statistical Modeling, Analysis and Optimization for Analog and RF ICs,” May 2005.
  30. Yang Xu, “Affordable Analog and Radio Frequency Integrated Circuits Design and Optimization,” December 2004.
  31. Satrajit Gupta, “Modeling Inductive Couplings in Traditional and Nanoscale Interconnects,” May 26, 2004.
  32. Peng Li, “Analysis and Macromodeling Continuum for Analog and RF ICs,” October 22, 2003.
  33. Aneesh Koorapaty, “Modular, Fabric-Specific Synthesis and Heterogeneous Logic Block Architectures for Regular Fabrics,” August 2003.
  34. Hui Zheng, “Efficient Modeling and Analysis for IC Power/Ground Distribution,” June 2003.
  35. Emrah Acar, “Linear Centric Simulation Approach for Timing Analysis,” November 2001.
  36. Davide Pandini, “Congestion Aware Logic Synthesis,” June 2001 (Co-advised by Professor A. Strojwas).
  37. Ravishankar Arunachalam, “Static Timing Analysis of Capactively Coupled Circuits,” November 2000.
  38. Michael Beattie, “Efficient Electromagnetic Modeling for Gigascale IC Interconnect,” August 2000.
  39. Frank (Ying) Liu, “Statistical Interconnect Analysis for CMOS Technologies,” September 1999 (Co-advised by Professor A. Strojwas).
  40. Altan Odabasioglu, “PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm,” September 1999.
  41. Zhijiang (John) He, “Fast Algorithms for 3D Inductance Extraction,” May 1999.
  42. Florentin Dartu, “Gate and Transistor Level Waveform Calculation for Timing Analysis,” August 1997.
  43. Byron Krauter, “Formulating Sparse Partial Inductance Matrices,” December 1995.
  44. Rohini Gupta, “Synthesis of High-Speed VLSI Interconnects,” August 1995.
  45. Noel Menezes, “Algorithms for RC Interconnect Synthesis,” May 1995.
  46. Satyamurthy Pullela, “Reliable Interconnect Design for On-Chip Clock Distribution,” December 1994.
  47. Seok-Yoon Kim, “Time-Domain Macromodels of VLSI System Interconnects,” June 1993.
  48. Dah Cherng Yuan , “Circuit Theoretical Switch Level Simulation Techniques in Mixed-Level Logic Simulation,” December 1992. (Co-advised by Professor J. Rahmeh)
  49. Douglas Holberg, “Efficient Gate Delay Models for Synthesis and Timing Analysis,” July 1992.
  50. Nanda Gopal, “Fast Evaluation of VLSI Interconnect Structures Using Moment Matching Meth­ods,” June 1992.