D. Morris, K. Vaidyanathan, N. Lafferty, K. Lai, L. Liebmann, L. Pileggi, “Design of Embedded Memory and Logic Based On Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2011.
S. Yaldiz, F. Wang, X. Li, L. Pileggi, A.S. Natarajan, M.A. Ferriss, J. Tierno, “Virtual Phase Noise Sensor for Self-Healing Voltage Controlled Oscillators”, GOMACTech-11 Technical Program, March 2011.
V. Rovner, T. Jhaveri, Daniel Morris, Andrzej J. Strojwas, and Larry Pileggi, “Performance and Manufacturability Trade-offs of Pattern Minimization for sub-22nm Technology Nodes”, SPIE Advanced Lithography Conference, February 2011.
G. Keskin, J. Proesel and L. Pileggi, “Statistical Modeling and Post Manufacturing Configuration for Scaled Analog CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2010.
A. Bonnoit, S. Herbert and L. Pileggi, “Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing”, International Symposium on Low Power Electronics and Design, August 2010.
G. Keskin, J. Proesel and L. Pileggi, “Modeling of Statistical Element Selection Based Self-Healing Analog Circuits”, Proceedings of the SRC Techcon Conference, September 2010.
D. Morris, S. Rovner, L. Pileggi, A. Strojwas and K. Vaidyanathan, “Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2010.
Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry Pileggi, Andrzej Strojwas, Jason D. Hibbeler, “Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, Invited Keynote Paper”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, April 2010.
L. Liebmann, J. Hibbeler, N. Hieter, L. Pileggi, M. Moe, T. Jhaveri, V. Rovner, “Demonstrating the benefits of template-based design-technology co-optimization”, SPIE Advanced Lithography Conference, February 2010.
T. Jhaveri, U. Urslan, V. Rovner, L. Pileggi & A. J. Strojwas, “Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization”, SPIE Advanced Lithography Conference, Selected for Keynote Presentation, February 2010.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774