Mismatch Analysis and Statistical Design at 65 nm and Below
L. Pileggi, G. Keskin, X. Li, K. Mai and J. Proesel, “Mismatch Analysis and Statistical Design at 65 nm and Below”, Invited Paper, Int’l Custom Integrated Circuits Conference, Sept. 2008.
Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers
/0 Comments/in Conference, Electronic Design Automation, Integrated Circuits, Publications /by awpG. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.
Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpXin Li, Jiayong Le, Mustafa Celik and Lawrence Pileggi, “Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations”, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 6, pp. 1041-1054, June 2008.
Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpE. Small, S.M. Sadeghipour, L. Pileggi, M. Asheghi, “Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM)”, ITherm, May 2008.
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpXin Li, Yaping Zhan and Lawrence Pileggi, “Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 831-843, May 2008.
Enabling Technology Scaling with ‘In Production’ Lithography Processes
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpT. Jhaveri, A.J. Strojwas, L. Pileggi, V. Rovner, “Enabling Technology Scaling with ‘In Production’ Lithography Processes”, SPIE Advanced Lithography Conference, February 2008.
Automated Testability Enhancements for Logic Brick Libraries
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpJ. Brown, B. Taylor, R. D. Blanton, and L. Pileggi, “Automated Testability Enhancements for Logic Brick Libraries”, Proceedings of Design and Test Europe, March 2008.
Digital circuit design challenges and opportunities in the era of nanoscale CMOS
/0 Comments/in Electronic Design Automation, Integrated Circuits, Peer Reviewed, Publications /by awpBenton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS”, Proceedings of The IEEE (PTI), vol. 96, no. 2, pp. 343-365, February 2008.
Exact Methods for Physical Design of Regular Logic Bricks
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpB. Taylor and L. Pileggi, “Exact Methods for Physical Design of Regular Logic Bricks”, Proceedings of the SRC Techcon Conference, October 2007.
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpX. Li, B. Taylor, Y-T. Chen and L. Pileggi, “Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization” , Proceedings of the International Conference on Computer-Aided Design, November 2007.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774