Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction

Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.

Design Automation Framework for Application-Specific Logic-in-Memory Blocks

Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, “Design Automation Framework for Application-Specific Logic-in-Memory Blocks”, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.

Statistical Design and Optimization for Adaptive Post-Silicon Tuning of MEMS Filters

F. Wang, G. Keskin, A. Phelps, J. Rotner, X. Li, G. Fedder, T. Mukherjee and L. Pileggi, “Statistical Design and Optimization for Adaptive Post-Silicon Tuning of MEMS Filters”, IEEE/ACM Design Automation Conference (DAC), 2012.

Design and Manufacturability Tradeoffs in Unidirectional & Bidirectional Standard Cell Images in 14 nm

K. Vaidyanathan, S.H. NG, D. Morris, N. Lafferty, L. Liebmann, W. Huang, K. Lai, L. Pileggi, A.J. Strojwas, “Design and Manufacturability Tradeoffs in Unidirectional & Bidirectional Standard Cell Images in 14 nm”, SPIE Advanced Lithography Conference, February 2012.

Local Loops for Robust Inter-Layer Routing at Sub-20 nm Nodes

W. Huang, D. Morris, N. Lafferty, L. Liebmann, K. Vaidyanathan, K. Lai, L. Pileggi, A.J. Strojwas, “Local Loops for Robust Inter-Layer Routing at Sub-20 nm Nodes”, SPIE Advanced Lithography Conference, February 2012.

Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization

M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li, and L. Pileggi, “Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization”, Communications of the ACM (invited paper), 2012.

Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization

M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li and L. Pileggi, “Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization”, Int’l Conference on Computer-Aided Design (Best Paper Award), November 2011.

Post-Silicon Calibration of Analog CMOS Using Phase-Change Memory Cells

C.-Y. Wen, J. Paramesh, L. T. Pileggi, J. Li, S. Kim, J. Proesel, C. Lam, “Post-Silicon Calibration of Analog CMOS Using Phase-Change Memory Cells”, European Solid-State Device Research Conference (ESSDERC), September 2011.

Using Continuization in Reachability Analysis for the Verification of a Phase-Locked Loop

M. Althoff, A. Rajhans, B.H. Krogh, S. Yaldiz, X. Li, L. Pileggi, “Using Continuization in Reachability Analysis for the Verification of a Phase-Locked Loop”, In Proc. Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.

Design Without Rules: A Pattern Construct Methodology

D. Morris, K. Vaidyanathan and L. Pileggi, “Design Without Rules: A Pattern Construct Methodology”, Proceedings of the SRC Techcon Conference, September 2011.