The Elmore Delay as a Bound for RC Trees with Generalized Input Signals

Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.

Modeling Lossy Transmission lines Using the Method of Characteristics

Rohini Gupta and Lawrence Pileggi, “Modeling Lossy Transmission lines Using the Method of Characteristics”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.

Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design

S. Pullela, N. Menezes and L.T. Pileggi, “Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design”, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.

Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach

Rohini Gupta, John Willis and Lawrence T. Pileggi, “Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach”, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.

Performance Computation for Pre-characterized CMOS Gates with RC Loads

F. Dartu, N. Menezes and L.T. Pileggi, “Performance Computation for Pre-characterized CMOS Gates with RC Loads”, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.

Domain Characterization of Transmission Line Models and Analyses

Rohini Gupta, Seok-Yoon Kim and Lawrence Pileggi, “Domain Characterization of Transmission Line Models and Analyses”, IEEE Transactions on Computer-Aided Design, pp. 184-193, February 1996.

Effective Capacitance

J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.

Time-Domain Macromodels for VLSI Interconnect Analysis

S.Y. Kim, N. Gopal and L.T. Pillage, “Time-Domain Macromodels for VLSI Interconnect Analysis”, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.

RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation

C. Ratzlaff and L.T. Pillage, “RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 763-776, June 1994.

On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation

D.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, “On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation”, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.