TETA: Transistor level Waveform Evaluation for Timing Analysis

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E. Acar, F. Dartu and L. T. Pileggi, “TETA: Transistor level Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.

Overcoming Wireload Model Uncertainty for Physical Design

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P. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, “Overcoming Wireload Model Uncertainty for Physical Design”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January 2002.

ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits

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Y. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.

Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI

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R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.

Equipotential Shells for Efficient Inductance Extraction

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M. Beattie, B. Krauter, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.

Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees

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M. Celik and L. T. Pileggi, “Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.

Bounds for BEM Capacitance Extraction

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M. Beattie and L. T. Pileggi, “Bounds for BEM Capacitance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.

Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers

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Rohini Gupta, John Willis and L.T. Pileggi, “Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers”, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.

PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm

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A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.