IEEE Journal of Solid State Circuits
Y. Xu, C. Boone and L. Pileggi, “IEEE Journal of Solid State Circuits”, Volume: 39, Issue: 8, pp. 1347-1351, Aug. 2004.
ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpYang Xu, Larry Pileggi, Stephan Boyd, “ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction”, August 2004
Parasitic Extraction with Multipole Refinement
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpM. Beattie and L.T. Pileggi, “Parasitic Extraction with Multipole Refinement”, IEEE Transactions on Computer-Aided Design, Vol. 23, (5 pages), February 2004.
Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpP. Li and L. T. Pileggi, “Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.
Electrical Modeling of Integrated-Package Power/Ground Distributions
/0 Comments/in Electronic Design Automation, Integrated Circuits, Peer Reviewed, Publications /by awpH. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
Global and Local Congestion Optimization in Technology Mapping
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpD. Pandini, L. T. Pileggi and A.J. Strojwas, “Global and Local Congestion Optimization in Technology Mapping”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 4, pp. 498-506, April 2003.
On-Chip Induction Modeling: Basics and Advanced Methods
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpM. Beattie and L.T. Pileggi, “On-Chip Induction Modeling: Basics and Advanced Methods”, Special Issue of IEEE Transactions on VLSI Systems, vol. 10, No. 6, pp. 712-729, December 2002.
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpR. Arunachalam, R. D. Blanton, L. T. Pileggi, “Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation”, VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, May 2002.
TETA: Transistor level Waveform Evaluation for Timing Analysis
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpE. Acar, F. Dartu and L. T. Pileggi, “TETA: Transistor level Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.
Overcoming Wireload Model Uncertainty for Physical Design
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpP. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, “Overcoming Wireload Model Uncertainty for Physical Design”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January 2002.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774