Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler

M. Celik and L. T. Pileggi, “Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.

A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing

N. Menezes, R. Baldick and L.T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing”, IEEE Transactions on Computer- Aided Design, August 1997.

Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets

S. Pullela, N. Menezes and L.T. Pileggi, “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.

Transmission Line Synthesis via Constrained Multivariable Optimization

Rohini Gupta, Byron Krauter and Lawrence Pileggi, “Transmission Line Synthesis via Constrained Multivariable Optimization”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.

The Elmore Delay as a Bound for RC Trees with Generalized Input Signals

Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.

Modeling Lossy Transmission lines Using the Method of Characteristics

Rohini Gupta and Lawrence Pileggi, “Modeling Lossy Transmission lines Using the Method of Characteristics”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.

Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design

S. Pullela, N. Menezes and L.T. Pileggi, “Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design”, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.

Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach

Rohini Gupta, John Willis and Lawrence T. Pileggi, “Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach”, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.

Performance Computation for Pre-characterized CMOS Gates with RC Loads

F. Dartu, N. Menezes and L.T. Pileggi, “Performance Computation for Pre-characterized CMOS Gates with RC Loads”, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.

Domain Characterization of Transmission Line Models and Analyses

Rohini Gupta, Seok-Yoon Kim and Lawrence Pileggi, “Domain Characterization of Transmission Line Models and Analyses”, IEEE Transactions on Computer-Aided Design, pp. 184-193, February 1996.