Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits

P. Li and L. T. Pileggi, “Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.

Electrical Modeling of Integrated-Package Power/Ground Distributions

H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.

Global and Local Congestion Optimization in Technology Mapping

D. Pandini, L. T. Pileggi and A.J. Strojwas, “Global and Local Congestion Optimization in Technology Mapping”, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 4, pp. 498-506, April 2003.

On-Chip Induction Modeling: Basics and Advanced Methods

M. Beattie and L.T. Pileggi, “On-Chip Induction Modeling: Basics and Advanced Methods”, Special Issue of IEEE Transactions on VLSI Systems, vol. 10, No. 6, pp. 712-729, December 2002.

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

R. Arunachalam, R. D. Blanton, L. T. Pileggi, “Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation”, VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, May 2002.

TETA: Transistor level Waveform Evaluation for Timing Analysis

E. Acar, F. Dartu and L. T. Pileggi, “TETA: Transistor level Waveform Evaluation for Timing Analysis”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.

Overcoming Wireload Model Uncertainty for Physical Design

P. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, “Overcoming Wireload Model Uncertainty for Physical Design”, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January 2002.

ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits

Y. Liu, L. T. Pileggi and A.J. Strojwas, “ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits”, IEEE Transactions on Circuits and Systems, April 2001.

Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI

R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, “Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI”, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.

Equipotential Shells for Efficient Inductance Extraction

M. Beattie, B. Krauter, L. Alatan and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.