From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography

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I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).

A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks

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S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.

Robust Power Flow and Three Phase Power Flow Analyses

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A. Pandey, M. Jereminov, M. R. Wagner, D. M. Bromberg, G. Hug, L. Pileggi, Robust Power Flow and Three Phase Power Flow Analyses, IEEE Transactions on Power Systems, Vol. 34, Issue:1, pp. 616-626, January 2019.

Equivalent Circuit Formulation for Solving AC Optimal Power Flow

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M. Jereminov, A. Pandey, L. Pileggi, Equivalent Circuit Formulation for Solving AC Optimal Power Flow, IEEE Transactions on Power Systems, December 2018.

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.

Application and Product-Volume Specific Customization of BEOL Metal Pitch

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “Application and Product-Volume Specific Customization of BEOL Metal Pitch,” IEEE Transactions on VLSI, Vol. 26, Issue:9, pp. 1627-1636, September 2018.

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

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S. Liu, T. Rabuske, J. Paramesh, L. Pileggi, and J. Fernandes, “Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs”, IEEE Transactions on Circuits and Systems I, Vol. 65, No. 2, pp. 458-470, February 2018.

Ultra-Compact Graphene Multigate Variable Resistor for Neuromorphic Computing

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M. Darwish, V. Calayir, L. Pileggi, J. Weldon, “Ultra-Compact Graphene Multigate Variable Resistor for Neuromorphic Computing”, IEEE Transactions on Nanotechnology, Vol. 15, No. 2, March 2016.

Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC

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R. Liu and L. Pileggi, “Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC”, IEEE Transactions on Circuits and Systems II, vol 62, no. 7, pp. 651-655, July 2015.