Sensitivity Analysis of Locked Circuits

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Sweeney, M. J. H. Heule, and L. Pileggi. “Sensitivity Analysis of Locked Circuits,” 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning (LPAR-23), May 2020.

A LASSO-Inspired Approach for Localizing Power System Infeasibility

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S. Li, A. Pandey, and L. Pileggi, “A LASSO-Inspired Approach for Localizing Power System Infeasibility,” IEEE PES General Meeting, Montreal, Canada, August 2020.

Robust Event-Driven Dynamic Simulation using Power Flow

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A. Agrawal, A. Pandey, and L. Pileggi, Robust Event-Driven Dynamic Simulation using Power Flow, IEEE Power Systems Computation Conference (PSSC), June 2020.

Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation

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Jovicic, M. Jereminov, L. Pileggi, Gabriela Hug, Enhanced Modelling Framework for Equivalent Circuit-Based Power System State Estimation, IEEE Transactions on Power Systems, February 2020 (10.1109/TPWRS.2020.2974459).

Evaluating Feasibility within Power Flow

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Jereminov, D.M. Bromberg, A. Pandey, M.R. Wagner, and L. Pileggi, “Evaluating Feasibility within Power Flow,” IEEE Transactions on Smart Grid, Vol. 11, No. 4, July 2020. DOI: 10.1109/TSG.2020.2966930.

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

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M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)

Steady-State Simulation for Combined Transmission and Distribution Systems

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A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, Vol 11, Issue 2, March 2020. (DOI: 10.1109/TSG.2019.2932403).

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography

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I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).

Latch-Based Logic Locking

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J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.