Integrated Circuits – Page 7

mLogic: All Spin Logic Device and Circuits for Future Electronics

May 3, 2014/0 Comments/in Conference, Integrated Circuits, Publications /by awp

J.-G. Zhu, D. Bromberg, V. Sokalski, M.T. Moneck, J. Wu, Z. Dai, L. Pileggi, “mLogic: All Spin Logic Device and Circuits for Future Electronics”, IEEE Transactions on Magnetics, INTERMAG 2014.

A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

February 1, 2014/0 Comments/in Conference, Integrated Circuits, Publications /by awp

V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, International Solid State Circuits Conference (ISSCC), February 2014.

Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers

January 1, 2014/0 Comments/in Conference, Electronic Design Automation, Integrated Circuits, Publications /by awp

J. Tao, Y.-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, L. Pileggi, “Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers”, 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014.

A Phase-Change Via-Reconfigurable CMOS LC VCO

December 1, 2013/0 Comments/in Integrated Circuits, Peer Reviewed, Publications /by awp

C.Y. Wen, G. Slovin, J. Bain, E. Schlesinger, L. Pileggi and J. Paramesh, “A Phase-Change Via-Reconfigurable CMOS LC VCO”, IEEE Transactions on Electron Devices, Vol. 60, No. 12, pp 3979-3988, December 2013.

Spintronic Devices and Circuits for Low-Voltage Logic

December 1, 2013/0 Comments/in Integrated Circuits, Peer Reviewed, Publications /by awp

D.H. Morris, D.M. Bromberg, J-G. ZHU and L. Pileggi, “Spintronic Devices and Circuits for Low-Voltage Logic”, International Journal of High Speed Electronics and Systems Vol. 21, No. 1 (2012) 1250005.

A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing

October 1, 2013/0 Comments/in Conference, Integrated Circuits, Publications /by awp

Qiuling Zhu, Berkin Akin, H. Ekin Sumbul, James C. Hoe, Larry Pileggi, Franz Franchetti, “A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing”, IEEE International 3D Systems Integration Conference, October 2013.

A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication

September 1, 2013/0 Comments/in Conference, Integrated Circuits, Publications /by awp

Qiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry Pileggi, Franz Franchetti, “A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication”, Seventeenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory (Best Paper Award), September 2013.

mLogic: All Spin Logic Device and Circuits for Future Electronics

A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers

A Phase-Change Via-Reconfigurable CMOS LC VCO

Spintronic Devices and Circuits for Low-Voltage Logic

A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing

A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication

All-Magnetic Analog Associative Memory

Neurocomputing and Associative Memories Based on Ovenized Aluminum Nitride Resonators

An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI

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