High Performance, Integrated 1T1R Oxide-based Oscillator: Stack Engineering for Low-Power Operation in Neural Network Applications

A. Sharma, T. Jackson, J. Bain, L. Pileggi and J. Weldon, “High Performance, Integrated 1T1R Oxide-based Oscillator: Stack Engineering for Low-Power Operation in Neural Network Applications”,in IEEE Symp. VLSI Technology, June 2015.

Application-Specific Synthesis of Embedded Logic-in-Memory Designs

H.E. Sumbul, K. Vaidyanathan, Q. Zhu, F. Franchetti, L. Pileggi, “Application-Specific Synthesis of Embedded Logic-in-Memory Designs”, manuscript accepted for publishing in Design Automation Conference (DAC 2015), June 2015.

3D Integration of AlN MEMS Filters and CMOS for Self-Healing RF Front-Ends

E. Calayir, J. Xu, A. Patterson, G. K. Fedder, G. Piazza, L. Pileggi, “3D Integration of AlN MEMS Filters and CMOS for Self-Healing RF Front-Ends”,Government Microcircuit Applications and Critical Technology Conference, March 2015.

An RRAM-Based Oscillatory Neural Network

T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, and L. Pileggi, “An RRAM-Based Oscillatory Neural Network”,in Proc. 2015 Latin American Symposium on Circuits and Systems. Montevideo, Uruguay, 2015.

3D-Stacked Memory-Side Acceleration: Accelerator and System Design

Q. Guo, N. Alachiotis, B. Akin, F. Sadi, G. Xu, T.M. Low, L. Pileggi, J.C. Hoe, and F. Franchetti, “3D-Stacked Memory-Side Acceleration: Accelerator and System Design”, WoNDP: 2nd Int’l Workshop on Near-Data Processing, December 2014.

Analog Neuromorphic Computing Enabled by Multi-Gate Programmable Resistive Devices, Design and Test in Europe

V. Calayir, M.Darwish, J. Weldon and L. Pileggi, “Analog Neuromorphic Computing Enabled by Multi-Gate Programmable Resistive Devices, Design and Test in Europe” (DATE), March 2015.

All-Magnetic MRAM Based on Four Terminal mCell Device

D. M. Bromberg, H. E. Sumbul, J.-G. Zhu, L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device”, Journal of Applied Physics, May 2015.

A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, Special Issue of the IEEE Journal on Solid State Circuits (Invited Paper), vol.49, no.12, pp.2891,2901, Dec. 2014.

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits

S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J.-O. Plouchart, B. Sadhu, B. Parker, A. Valdes Garcia, M.A.T. Sanduleanu, J. Tierno, and D. Friedman, “Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits”, IEEE Transactions on Circuits and Systems, vol.61, no.8, pp.2243,2252, Aug. 2014.

Design Implications of Extremely Restricted Patterning

K. Vaidyanathan, R. Liu, L. Liebmann, K. Lai, A. Strojwas, L. Pileggi, “Design Implications of Extremely Restricted Patterning”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 13 (03), 2014.