A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI

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V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI”, Special Issue of the IEEE Journal on Solid State Circuits (Invited Paper), vol.49, no.12, pp.2891,2901, Dec. 2014.

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits

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S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J.-O. Plouchart, B. Sadhu, B. Parker, A. Valdes Garcia, M.A.T. Sanduleanu, J. Tierno, and D. Friedman, “Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits”, IEEE Transactions on Circuits and Systems, vol.61, no.8, pp.2243,2252, Aug. 2014.

Design Implications of Extremely Restricted Patterning

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K. Vaidyanathan, R. Liu, L. Liebmann, K. Lai, A. Strojwas, L. Pileggi, “Design Implications of Extremely Restricted Patterning”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 13 (03), 2014.

Experimental Demonstration of Four-Terminal Magnetic Logic Device with Separate Read- and Write-Paths, International Electron Devices Meeting

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D. Bromberg, M. Moneck, V. Sokalski, L. Pileggi, J-G. Zhu, “Experimental Demonstration of Four-Terminal Magnetic Logic Device with Separate Read- and Write-Paths, International Electron Devices Meeting”, December 2014.

All-Magnetic MRAM Based on Four Terminal mCell Device

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D.M. Bromberg, E. Sumbul, J-G. Zhu and L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device”, 13th Joint MMM/Intermag Conference, November 2014.

Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory

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F. Sadi, B. Akin, D. Popovici, J. Hoe, L. Pileggi, F. Franchetti, “Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory”, Eighteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2014.

A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio

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R. Liu, L. Pileggi and J. Weldon, “A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio”, Int’l Custom Integrated Circuits Conference, September 2014.

Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic

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K. Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi, “Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic”, Int’l Conference on Computer-Aided Design, November 2014.

Integrating Emerging Devices and CMOS for Efficient Cellular Neural Networks

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T. Jackson, V. Calayir and L. Pileggi, “Integrating Emerging Devices and CMOS for Efficient Cellular Neural Networks”, Proceedings of the SRC Techcon Conference, September 2014.

Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits

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M. T. Moneck, V. Sokalski, D. M. Bromberg, J. Wu, Z. Dai, L. Pileggi, J.-G. Zhu, “Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits”, 2014 International Magnetics Conference.