From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization

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F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.

A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks

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S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.

Application and Product-Volume Specific Customization of BEOL Metal Pitch

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “Application and Product-Volume Specific Customization of BEOL Metal Pitch,” IEEE Transactions on VLSI, Vol. 26, Issue:9, pp. 1627-1636, September 2018.

An Oscillatory Neural Network with Programmable Resistive Synapses

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T. Jackson, S. Pagliarini and L. Pileggi, “An Oscillatory Neural Network with Programmable Resistive Synapses,” in 28 nm CMOS, IEEE International Conference on Rebooting Computing, November 2018.

A 125 Ms/S 10.4 ENOB 10.1 fJ/conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS

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S. Liu, T. Rabuske, L. Pileggi, J. Fernandez, J. Paramesh, “A 125 Ms/S 10.4 ENOB 10.1 fJ/conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS,” IEEE European Solid-State Circuits conference, September 2018.

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

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S. Liu, T. Rabuske, J. Paramesh, L. Pileggi, and J. Fernandes, “Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs”, IEEE Transactions on Circuits and Systems I, Vol. 65, No. 2, pp. 458-470, February 2018.

Self-healing Narrowband Filters via 3D Heterogeneous Integration of AlN MEMS and CMOS chips

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E. Calayir, J. Xu, L. Pileggi, G. K. Fedder, N. Singh, S. Merugu and G. Piazza, “Self-healing Narrowband Filters via 3D Heterogeneous Integration of AlN MEMS and CMOS chips”, 2017 IEEE International Ultrasonics Symposium (IUS), Washington, D.C., September 2017.