U. Arslan, M. McCartney, M. Bhargava, L. Pileggi and K. Mai, “Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines”, Proceedings of the SRC Techcon Conference, September 2008.
J. Proesel and L. Pileggi, “A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS”, Proceedings of the SRC Techcon Conference, September 2008.
G. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.
Benton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS”, Proceedings of The IEEE (PTI), vol. 96, no. 2, pp. 343-365, February 2008.
P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.
Y. Xu and L. Pileggi, “Metal-mask Configurable RF Integrated Circuits”, GOMACTech-05 Technical Program, April 2005.
H. Zheng, B. Krauter and L.T. Pileggi, “Electrical Modeling of Integrated-Package Power/Ground Distributions”, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
H. Zheng, B. Krauter, L. Pileggi, “On-Package Decoupling Optimization with Package Macromodels”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
K.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
A. Koorapaty, L. Pileggi, H. Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics”, International Conference on Field Programmable Logic and Applications, September 2003.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774