Economic Assessment of Lithography Strategies for the 22nm Technology Node

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T. Jhaveri, A. J. Strojwas, L. Pileggi and V. Rovner, “Economic Assessment of Lithography Strategies for the 22nm Technology Node”, Proceedings of the SPIE/BACUS Symposium on Photomask Technology, September 2009.

OPC Simplification & Mask Cost Reduction using Regular Design Fabrics

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Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner, “OPC Simplification & Mask Cost Reduction using Regular Design Fabrics”, SPIE Advanced Lithography Conference, February 2009.

Ring Oscillators for Single Process-Parameter Monitoring

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Bin Wan, Jian Wang, Gokce Keskin, and Lawrence T. Pileggi, “Ring Oscillators for Single Process-Parameter Monitoring”, IEEE Workshop on Test Structure Design for Variability Characterization, November 2008.

A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS

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J. Proesel and L. Pileggi, ‘A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS’, Int’l Custom Integrated Circuits Conference, Sept. 2008.

Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines

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U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai and L. Pileggi, “Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines”, Int’l Custom Integrated Circuits Conference, Sept. 2008.

Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines

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U. Arslan, M. McCartney, M. Bhargava, L. Pileggi and K. Mai, “Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines”, Proceedings of the SRC Techcon Conference, September 2008.

A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS

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J. Proesel and L. Pileggi, “A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS”, Proceedings of the SRC Techcon Conference, September 2008.

Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers

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G. Keskin, L. Pileggi, X. Li and K. Mai, “Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers”, Proceedings of the SRC Techcon Conference, September 2008.

Digital circuit design challenges and opportunities in the era of nanoscale CMOS

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Benton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS”, Proceedings of The IEEE (PTI), vol. 96, no. 2, pp. 343-365, February 2008.

Timing Driven Initial Placement for FPGAs via Graph Matching

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P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.