An IP-Agnostic Foundational Cell Array Offering Supply Chain Security
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “An IP-Agnostic Foundational Cell Array Offering Supply Chain Security,” The 61st Design Automation Conference, June 2024.
IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpC. Talbot, Deepali Garg, L. Pileggi and K. Mai, “IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2024.
Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpD. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
High Performance Merge Sort with Scalable Parallelization and Full-Throughput Reduction
/in Integrated Circuits, Publications /by awpU.S. Patent No. – High Performance Merge Sort with Scalable Parallelization and Full-Throughput Reduction – Sadi, Franchetti, Pileggi, October 27, 2021.
Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design
/in Integrated Circuits, Publications, Secure Hardware /by awpD. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpP. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.
Top-down physical design of soft embedded FPGA fabrics
/in Integrated Circuits, Publications, Secure Hardware /by awpP. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.
A Multiplexed Active Digital Implantable Neural Probe
/in Conference, Integrated Circuits, Publications /by awpX. He, S. Liu, S. Kargarrazi, V. Chen, M. Chamanzar, L. Pileggi, “A Multiplexed Active Digital Implantable Neural Probe,” In proceedings of SfN Global Connectome (virtual conference), January 11-13, 2021.
Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpP. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes
/in Integrated Circuits, Peer Reviewed, Publications /by awpM. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774