R. Gupta, S.Y. Kim and L.T. Pillage, “Domain Characterization of Transmission Line Models for Efficient Simulation”, Proceedings of the International Conference on Computer Design, October 1994.
R. Gupta and L.T. Pillage, “OTTER: Optimal Termination of Transmission Lines Excluding Radiation”, Proceedings Design Automation Conference, June 1994.
F. Dartu, N. Menezes, J. Qian and L.T. Pillage, “A Gate Delay Model for High Performance CMOS”, Proceedings Design Automation Conference, June 1994.
R.B. Brashear, N. Menezes, C. Oh, L.T. Pillage and M.R. Mercer, “Predicting Circuit Performance Using Circuit-Level Statistical Timing Analysis”, Proceedings of the European Design Automation Conference, February 1994.
S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Skew and Delay Optimization for Reliable Buffered Clock Trees”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
E. Tuncer, S.Y. Kim, L.T. Pillage and D. Neikirk, A New, “Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, October 1993.
D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, “Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation”, Proceedings Design Automation Conference, June 1993.
S. Pullela, N. Menezes and L.T. Pillage, “Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization”, Proceedings Design Automation Conference, June 1993.
S.Y. Kim, N. Gopal and L.T. Pillage, “Finite-Pole Macromodels of Transmission Lines for Circuit Simulation”, Proceedings Custom Integrated Circuits Conference, May 1993.
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