A. Balivada, D. Holberg and L.T. Pillage, “Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation”, Proceedings Custom Integrated Circuits Conference, May 1991.
D. Holberg, S. Dutta and L.T. Pillage, “DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation”, Proceedings IEEE International Conference on Computer-Aided Design, November 1990.
S. Dutta and L.T. Pillage, “Calculating the Moments in AWE With Linear Complexity”, Proceedings of the SRC Techcon Conference, October 1990.
L.T. Pillage and S. Dutta, “A Path Tracing Algorithm for Asymptotic Waveform Evaluation of RLC Circuit Delay Models”, 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990.
L.T. Pillage, X. Huang and R.A. Rohrer, “Asymptotic Waveform Evaluation for Circuits Containing Floating Nodes”, Proceedings IEEE International Symposium on Circuits and Systems, May 1990.
L.T. Pillage, X. Zhang and R.A. Rohrer, “Efficient Final Placement Based on Nets-as- Points”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, X. Huang and R.A. Rohrer, “AWEsim: Asymptotic Waveform Evaluation for Timing Analysis”, Proceedings Design Automation Conference, June 1989.
L.T. Pillage, C. Wolff and R.A. Rohrer, “Frequency Response Simulation”, Proceedings Custom Integrated Circuits Conference, May 1989.
L.T. Pillage and R.A. Rohrer, “Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models”, Proceedings Decennial Caltech Conference on VLSI, March 1989.
L.T. Pillage and R.A. Rohrer, “A Quadratic Metric for the Initial Placement Problem with a Simple Solution Scheme”, Proceedings Design Automation Conference, June 1988.
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