N. Menezes, R. Baldick and L. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing”, Proceedings of the International Conference on Computer-Aided Design, 1995.
B. Krauter and L. Pileggi, “Generating Sparse Partial Inductance Matrices with Guaranteed Stability”, Proceedings of the International Conference on Computer-Aided Design, 1995.
L. Pileggi, “Coping with RC(L) Interconnect Induced Headaches”, Proceedings of the International Conference on Computer-Aided Design, (Invited Tutorial Paper) 1995.
I. Tesu and L. Pileggi, “Pre-characterization of ECL Gates for Timing Analysis”, SCS ’95 International Symposium on Signals, Circuits & Systems, Iasi, Romania, October 1995.
S. Pullela, N. Menezes and L.T. Pillage, “Low Power IC Clock Tree Design”, Proceedings Custom Integrated Circuits Conference, May 1995.
B. Krauter, D. Neikirk and L.T. Pillage, “Sparse Partial Inductance Matrix Formulation”, Progress in Electromagnetics Research Symposium, July 1995.
Rohini Gupta, John Willis and L.T. Pillage, “Wire Width Optimization of Transmission Lines for Low Power Design”, IEEE Multi-chip Module Conference, February 1995.
L.T. Pillage and R.A. Rohrer, “The Essence of AWE”, Circuits and Devices Magazine, November 1994.
John Willis, Rohini Gupta and L.T. Pillage, “Metrics for RLC Transmission Line Termination”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1994.
N. Menezes, S. Pullela and L.T. Pillage, “RC Interconnect Synthesis — A Moment Fitting Approach”, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774