Sparse Partial Inductance Matrix Formulation
B. Krauter, D. Neikirk and L.T. Pillage, “Sparse Partial Inductance Matrix Formulation”, Progress in Electromagnetics Research Symposium, July 1995.
B. Krauter, D. Neikirk and L.T. Pillage, “Sparse Partial Inductance Matrix Formulation”, Progress in Electromagnetics Research Symposium, July 1995.
Rohini Gupta, John Willis and L.T. Pillage, “Wire Width Optimization of Transmission Lines for Low Power Design”, IEEE Multi-chip Module Conference, February 1995.
L.T. Pillage and R.A. Rohrer, “The Essence of AWE”, Circuits and Devices Magazine, November 1994.
John Willis, Rohini Gupta and L.T. Pillage, “Metrics for RLC Transmission Line Termination”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1994.
N. Menezes, S. Pullela and L.T. Pillage, “RC Interconnect Synthesis — A Moment Fitting Approach”, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
R. Gupta, S.Y. Kim and L.T. Pillage, “Domain Characterization of Transmission Line Models for Efficient Simulation”, Proceedings of the International Conference on Computer Design, October 1994.
R. Gupta and L.T. Pillage, “OTTER: Optimal Termination of Transmission Lines Excluding Radiation”, Proceedings Design Automation Conference, June 1994.
F. Dartu, N. Menezes, J. Qian and L.T. Pillage, “A Gate Delay Model for High Performance CMOS”, Proceedings Design Automation Conference, June 1994.
R.B. Brashear, N. Menezes, C. Oh, L.T. Pillage and M.R. Mercer, “Predicting Circuit Performance Using Circuit-Level Statistical Timing Analysis”, Proceedings of the European Design Automation Conference, February 1994.
S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules”, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
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