N. Menezes, S. Pullela and L. Pileggi, “Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization”, Proceedings of the Design Automation Conference, 1995.
R. Gupta, B. Krauter, B. Tutuianu, J. Willis and L. Pileggi, “The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals”, Proceedings of the Design Automation Conference, 1995.
R. Gupta and L. Pileggi, “Constrained Multivariable Optimization of Transmission Lines with General Topologies”, Proceedings of the International Conference on Computer-Aided Design, 1995.
N. Menezes, R. Baldick and L. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing”, Proceedings of the International Conference on Computer-Aided Design, 1995.
B. Krauter and L. Pileggi, “Generating Sparse Partial Inductance Matrices with Guaranteed Stability”, Proceedings of the International Conference on Computer-Aided Design, 1995.
L. Pileggi, “Coping with RC(L) Interconnect Induced Headaches”, Proceedings of the International Conference on Computer-Aided Design, (Invited Tutorial Paper) 1995.
I. Tesu and L. Pileggi, “Pre-characterization of ECL Gates for Timing Analysis”, SCS ’95 International Symposium on Signals, Circuits & Systems, Iasi, Romania, October 1995.
I. Tesu and L. Pileggi, “Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages”, Proceedings of the IEEE ASIC Conference, 1995.
B. Krauter, R. Gupta, J. Willis and L. Pileggi, “Transmission Line Synthesis”, Proceedings of the Design Automation Conference , 1995.
S. Pullela, N. Menezes and L.T. Pillage, “Low Power IC Clock Tree Design”, Proceedings Custom Integrated Circuits Conference, May 1995.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774