Looking Beyond the Elmore Delay — Metrics for Deep Submicron
T. Lin and L. Pileggi, “Looking Beyond the Elmore Delay — Metrics for Deep Submicron”, Proceedings of the SRC Techcon Conference, September 1998.
Equipotential Shells for Efficient Inductance Extraction
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpM. Beattie and L. Pileggi, “Equipotential Shells for Efficient Inductance Extraction”, Proceedings of the SRC Techcon Conference, September 1998.
TETA: Transistor-Level Engine for Timing Analysis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpFlorin Dartu and Lawrence Pileggi, “TETA: Transistor-Level Engine for Timing Analysis”, Proceedings of the Design Automation Conference, June 1998.
An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpFrank Liu, Lawrence Pileggi and Andrzej Strojwas, ftd: “An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models”, Proceedings of the Design Automation Conference, June 1998.
PRIMO: Probability Interpretation of Moments for Delay Calculation
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpRony Kay and Lawrence Pileggi, “PRIMO: Probability Interpretation of Moments for Delay Calculation”, Proceedings of the Design Automation Conference, June 1998.
Timing Metrics for Physical Design of Deep Submicron Technologies
/0 Comments/in Conference, Publications /by awpL. Pileggi, “Timing Metrics for Physical Design of Deep Submicron Technologies”, Invited paper, International Symposium on Physical Design, April 1998.
A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpZhijiang (John) He and Lawrence T. Pileggi, “A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds”, Proceedings of the Custom Integrated Circuits Conference, May 1998.
A Hierarchical Decomposition Methodology for Multistage Clock Circuits
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpG. Ellis, L.T. Pileggi, R.A. Rutenbar, “A Hierarchical Decomposition Methodology for Multistage Clock Circuits”, Proceedings of the International Conference on Computer-Aided Design, 1997.
PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpA. Odabasioglu, M. Celik, L.T. Pileggi, “PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm”, Proceedings of the International Conference on Computer-Aided Design, 1997.
Clustering and Load Balancing for Buffered Clock Tree Synthesis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpA. Mehta, Y-P. Chen, N. Menezes, L. T.Pileggi and M. Wong, “Clustering and Load Balancing for Buffered Clock Tree Synthesis”, Proceedings of the Int’l Conference on Computer Design, October 1997.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774