G. Ellis, L. Pileggi and R. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
F. Liu, L. Pileggi and A.J. Strojwas, “A Sparse Macromodeling Method for RC Interconnect Multiports”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
F. Dartu and L.T. Pileggi, “Gate-level modeling of of coupling capacitance effects”, Proceedings of the SRC Techcon Conference, October 1996.
Florentin Dartu and Lawrence T. Pileggi, “Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models”, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
Florin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, “RC-Interconnect Macromodels for Timing Simulation”, Proceedings of the Design Automation Conference , 1996.
Bogdan Tutuianu and Lawrence Pileggi, “An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response”, Proceedings of the Design Automation Conference , 1996.
Byron Krauter, Yu Xia, Aykut Dengi, Lawrence T. Pileggi, “A Sparse Image Method for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1996.
Xun Yang, Byron Krauter and L. Pileggi, “Combined ac and Transient Power Distribution Analysis”, Proceedings of the Custom Integrated Circuits Conference, May 1996.
R. Gupta, B. Krauter and L. Pileggi, “On Moment Based Metrics for Optimal Termination of Transmission Line Interconnects”, Proceedings of the 9th International Conference on VLSI Design, January 1996.
M. Kamon, B. Krauter, J. Phillips, L. Pileggi, and J. White, “Two Optimizations to Accelerated Method-of-Moments Algorithms for Signal Integrity Analysis of Complicated 3-D Packages”, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November 1995.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774