Florin Dartu and Lawrence Pileggi, “Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling”, Proceedings of the Design Automation Conference, 1997.
http://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.png00awphttp://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.pngawp1997-05-05 08:00:002019-02-13 10:58:31Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling
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