P. Gopalakrishnan and L. Pileggi, “Timing Driven Initial Placement for FPGAs via Graph Matching”, Proceedings of the SRC Techcon Conference, October 2005.
http://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.png00awphttp://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.pngawp2005-09-01 08:00:002019-02-13 13:50:44Timing Driven Initial Placement for FPGAs via Graph Matching
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