(Inactive Page) Does Hardware Design Have to be Hard?

Most of the materials has since made it into 18-643

Continued performance scaling must be accompanied by expending less energy per operation. Without Dennard scaling, mapping computation directly onto hardware—avoiding the execution overhead of software—is the most direct way to achieve the needed energy/power reduction for the most performance demanding applications. The increasingly capable FPGA co-processing options emerging in the last few years have reduced the barrier-to-entry from a platform perspective. Still, a major obstacle to a more widespread use of hardware acceleration remains in the high degree of difficulty in mapping applications to hardware.

This short course addresses the question, does hardware design have to be hard, especially in the context of mapping computation to hardware for acceleration. The scope of the course is based on the research experience and perspectives of the instructor. This course does not assume a background in digital logic design.

There will be approximately 2 hours of slide-based presentation and 1 hour of open discussion per day for this 5-day short course.

(Note: Most of the materials has since made it into 18-643)

• Introduction (slides)
• Essential Hardware Design Concepts (slides — CMU 18-100 L21~L25)
• Operation-Centric Hardware Design and Synthesis (Bluespec) (slides — project website — Bluespec)
• C-to-Hardware Design and Synthesis (slides — D&T Special Issue)
• Domain-Specialized High-level Synthesis (Spiral) (slides — project website — DFTgen)
• “Smart” IP-Based Design (Pandora) (slides — CONNECT NoC Generator)
• Infrastructure and Virtualization (CoRAM) (slides — project website — try it out)
• Performance, Power and Energy of Hardware Acceleration (slides — background reading)

James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University. He received his Ph.D. in EECS from Massachusetts Institute of Technology in 2000 (S.M., 1994). He received his B.S. in EECS from UC Berkeley in 1992. He is interested in many aspects of computer architecture and digital hardware design, including the specific areas of FPGA architecture for computing; digital signal processing hardware; and high-level hardware design and synthesis. He co-directs the Computer Architecture Lab at Carnegie Mellon (CALCM) and is affiliated with the Center for Silicon System Implementation (CSSI). He is a Fellow of IEEE.

For more than 15 years, Dr. Hoe has actively researched languages and tools to support hardware design and synthesis from a high-level of abstraction. Dr. Hoe’s PhD research investigated a novel “operation-centric” high-level hardware design abstraction and its synthesis. As a member of the SPIRAL project team at Carnegie Mellon since 2003, Dr. Hoe has led the project branch in creating an automatic hardware design compiler for linear transforms. Dr. Hoe's other significant research efforts occupy the intersection of reconfigurable logic and computer architecture. Between 2005 and 2010, Dr. Hoe researched FPGA-accelerated simulation technology to deliver the necessary simulation performance to enable full-scale software research on top of simulated experimental architectures. Dr. Hoe's current major research focus is on devising a new FPGA architecture for power efficient, high-performance computing.

For more information, please visit https://users.ece.cmu.edu/~jhoe.