Papers and Major Presentations

• HASTE: Hybrid Architectures with a Single, Transformable Executable, Ph.D.. Thesis, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, May 2005.
              [Paper: levine_phd_thesis.pdf - 12.4M PDF file]

• “Implementation of Target Recognition Applications Using Pipelined Reconfigurable Hardware,” presented at the Military and Aerospace Programmable Logic Devices International Conference (MAPLD),, September 2003.
          [Extended abstract: mapld03_piperench_abstract.pdf – 17K PDF file]
          [Presentation: mapld03_piperench_pres.pdf – 734K PDF file]

• “Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable,” in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2003, pp 101-110 (With H. Schmit). 
          [Paper: fccm03_haste.pdf – 699K PDF file]

•  “Hardware Compilation in Hardware: Enabling Integration of Reconfigurable Fabrics and Processors,” presented at the SRC GFP Conference, Dallas, TX, September 2002
  (presentation only). 
              [Presentation: SRC_GFP02_HASTE.pdf – 553K PDF file]

• “PipeRench: Power & Performance Evaluation of a Programmable Pipelined Datapath,” presented at Hot Chips 14, Palo Alto, CA, August 2002 (presentation only, with H. Schmit). 
              [Presentation: hotchips02_piperench.pdf – 1.9M PDF file]

• “PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology,” Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), 2002. (with H. Schmit, D. Whelihan, A. Tsai, M. Moe, R. R. Taylor). 
              [Paper: cicc02_piperench.pdf – 212K PDF file]

• “Queue Machines: Hardware Compilation in Hardware,” in IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), April 2002. (with H. Schmit, B. Ylvisaker )
              [Paper: fccm02_queue.pdf – 211K PDF file]

• “Implementation of Near Shannon Limit Error-Correction Codes Using Reconfigurable Hardware”, Proceedings of the 2000 IEEE Symposium on Field-programmable Custom Computing Machines (FCCM), pp. 217-226, Napa, CA, April 17-19, 2000. (with R.R. Taylor, H. Schmit.)
              [Paper: fccm00_ecc.pdf - 255K PDF file]

• “Automatic Mapping of Khoros-based Applications to Adaptive Computing Systems'”, Proceedings of 1999 Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD), pp. 101-107, Laurel, MD, Sept. 28-30, 1999. (with S. Natarajan, C. Tan, D. Newport,  D. Bouldin) 
              [Paper: mapld99_champion.pdf- 71K PDF file]

• “Training IP Creators and Integrators ”, Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), pp 12-13. (with S. Natarajan, C. Tan, D. Newport, D. Bouldin)
              [Paper: mse99_ip_creators.pdf – 47K PDF file]
• A System for the Implementation of Image Processing Algorithms on Configurable Computing Hardware, M.S. Thesis, Dept. of Electrical  Engineering, University of Tennessee, August 1999.
              [Paper: levine_ms_thesis.pdf - 421K PDF file]

• “Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-based Reconfigurable Hardware”, Proceedings of the 1999 IEEE Symposium on Field-programmable Custom Computing Machines (FCCM), pp. 292-293, Napa, CA, April 21-23, 1999. (Poster, with S. Natarajan, C. Tan, D. Newport, and D. Bouldin)
              [Extended abstract: fccm99_champion.pdf - 31K PDF file]