Description

With the continued off-shoring of advanced integrated circuit (IC) manufacturing facilities, the ability to fully secure the IC manufacturing supply chain is increasingly challenging. While commercial-off-the-shelf (COTS) programmable solutions such as FPGAs and microprocessors are a viable alternative to a custom ASIC (application specific integrated circuit), it is generally at a significant cost in terms of performance-at-power (PaP). Our research is toward developing methods to design and fabricate ICs in untrusted supply chains while keeping the sensitive IP from the manufacturer. We further consider techniques to mitigate a malicious third party’s ability to alter the design during manufacturing, along with making it more difficult for others to perform in-the-field reverse engineering of critical IP.

Lab Members

  • Joe Sweeney
    Graduate Student
    Secure IC Design Methodology
  • Mohammed Zackriya
    Research Scientist
    Secure IC Design

Recent Publications

  1. J. Sweeney, M. Zackriya, S. Pagliarini and L. Pileggi, Securing Digital Systems via Split-Chip Obfuscation, GOMACTech Technical Program, March 2019.

  2. K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, L. Pileggi, “Efficient and Secure Intellectual Property (IP) Design with Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.

  3. K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, L. Pileggi, “Building Trusted ICs using Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.

  4. K. Vaidyanathan, B. Prasad Das, L. Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack”, IEEE/ACM Design Automation Conference, June 2014.

  5. J. Tao, Y-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee and L. Pileggi, “Efficient System-Level Performance Modeling and Optimization for Reprogrammable Radio Frequency (RF) Systems”, Frontiers in Analog CAD Workshop, February 2013.