Description

With the continued off-shoring of advanced integrated circuit (IC) manufacturing facilities, the ability to fully secure the IC manufacturing supply chain is increasingly challenging. While commercial-off-the-shelf (COTS) programmable solutions such as FPGAs and microprocessors are a viable alternative to a custom ASIC (application specific integrated circuit), it is generally at a significant cost in terms of performance-at-power (PaP). Our research is toward developing methods to design and fabricate ICs in untrusted supply chains while keeping the sensitive IP from the manufacturer. We further consider techniques to mitigate a malicious third party’s ability to alter the design during manufacturing, along with making it more difficult for others to perform in-the-field reverse engineering of critical IP.

Lab Members

  • Deepali Garg
    Graduate Student
    Secure IC Design
  • Joe Sweeney
    Graduate Student
    Secure IC Design Methodology
  • Mohammed Zackriya
    Research Scientist
    Secure IC Design

Recent Publications

  1. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.

  2. S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra and L. Pileggi, “Split-Chip Design to prevent IP Reverse Engineering,” in IEEE Design & Test, doi: 10.1109/MDAT.2020.3033255.

  3. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.

  4. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.

  5. J. Sweeney, M.J.H. Heule, L. Pileggi, “Modeling Techniques for Logic Locking,” IEEE International Conference on Computer-Aided Design, November 2020.

  6. Sweeney, M. J. H. Heule, and L. Pileggi. “Sensitivity Analysis of Locked Circuits,” 23rd International Conference on Logic for Programming, Artificial Intelligence and Reasoning (LPAR-23), May 2020.

  7. I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).

  8. J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2020.

  9. J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2020.

  10. I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, (DOI: 10.1007/s41635-019-00080-y).