Description

While the end of CMOS scaling is now in sight, the advancement of integrated circuits and systems remains a top priority for the electronics industry. A significant portion of our research has been focused on methodologies that support affordable design in sub-20nm CMOS technologies, but much of that work also includes opportunistic integration of emerging heterogeneous technologies that are compatible with the CMOS. We further explore use of emerging materials and devices (e.g. magnetics, resistance change, phase change, etc.) that provide new computational or storage capabilities when configured in new forms, or applied to specific architectures. Several of our projects target specific system applications in domains such as brain and human interfaces.

Lab Members

  • Kai-Chun Li
    Graduate Student
    IoT Interface Circuits
  • Xi He
    Graduate Student
    Brain Probe Interface Circuits
  • Joe Sweeney
    Graduate Student
    Secure IC Design
  • Mohammed Zackriya
    Research Scientist
    Secure IC Design

Recent Publications

  1. F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.

  2. S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.

  3. S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.

  4. S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.

  5. S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “Application and Product-Volume Specific Customization of BEOL Metal Pitch,” IEEE Transactions on VLSI, Vol. 26, Issue:9, pp. 1627-1636, September 2018.

  6. T. Jackson, S. Pagliarini and L. Pileggi, “An Oscillatory Neural Network with Programmable Resistive Synapses,” in 28 nm CMOS, IEEE International Conference on Rebooting Computing, November 2018.

  7. S. Liu, T. Rabuske, L. Pileggi, J. Fernandez, J. Paramesh, “A 125 Ms/S 10.4 ENOB 10.1 fJ/conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS,” IEEE European Solid-State Circuits conference, September 2018.

  8. S. Liu, T. Rabuske, J. Paramesh, L. Pileggi, and J. Fernandes, “Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs”, IEEE Transactions on Circuits and Systems I, Vol. 65, No. 2, pp. 458-470, February 2018.

  9. E. Calayir, J. Xu, L. Pileggi, G. K. Fedder, N. Singh, S. Merugu and G. Piazza, “Self-healing Narrowband Filters via 3D Heterogeneous Integration of AlN MEMS and CMOS chips”, 2017 IEEE International Ultrasonics Symposium (IUS), Washington, D.C., September 2017.

  10. S. Bhuin, J. Sweeney, S. Pagliarini, A. K. Biswas, L. Pileggi, “A Self-Calibrating Sense Amplifier for A True Random Number Generator Using Hybrid FinFET-Straintronic MTJ”, IEEE International Symposium on Nanoscale Architectures (NANOARCH), July 2017.