Description

While the end of CMOS scaling is now in sight, the advancement of integrated circuits and systems remains a top priority for the electronics industry. A significant portion of our research has been focused on methodologies that support affordable design in sub-20nm CMOS technologies, but much of that work also includes opportunistic integration of emerging heterogeneous technologies that are compatible with the CMOS. We further explore use of emerging materials and devices (e.g. magnetics, resistance change, phase change, etc.) that provide new computational or storage capabilities when configured in new forms, or applied to specific architectures. Several of our projects target specific system applications in domains such as brain and human interfaces.

Lab Members

  • Cheng-De Lin
  • Yihan Ruan

Recent Publications

  1. A. Agarwal, R. Rohrer, and L. Pileggi, “Second-Order Optimization via Quiescence Trajectory Tracing,” IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2026.3689681.

  2. B.J. Gonzalez, Y. Chen, J. Kunselman, J.K. Wirant, Elio Bourcart, Matthew T. Moneck, Tathagata Srimani, L. Pileggi, The Hacker Fab: An Open-Source Initiative for Nanofabrication Education, International Symposium on Circuits and Systems (ISCAS), May 2026.

  3. D. Garg and L. Pileggi, Universal Topological Arrays: An Efficient Solution for Provably Secure Hardware, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 6-9, 2025.

  4. C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “An IP-Agnostic Foundational Cell Array Offering Supply Chain Security,” The 61st Design Automation Conference, June 2024.

  5. C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2024.

  6. D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.

  7. U.S. Patent No.  – High Performance Merge Sort with Scalable Parallelization and Full-Throughput Reduction – Sadi, Franchetti, Pileggi, October 27, 2021.

  8. D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.

  9. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.

  10. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.