Description

With the continued off-shoring of advanced integrated circuit (IC) manufacturing facilities, the ability to fully secure the IC manufacturing supply chain is increasingly challenging. While commercial-off-the-shelf (COTS) programmable solutions such as FPGAs and microprocessors are a viable alternative to a custom ASIC (application specific integrated circuit), it is generally at a significant cost in terms of performance-at-power (PaP). Our research is toward developing methods to design and fabricate ICs in untrusted supply chains while keeping the sensitive IP from the manufacturer. We further consider techniques to mitigate a malicious third party’s ability to alter the design during manufacturing, along with making it more difficult for others to perform in-the-field reverse engineering of critical IP.

Lab Members

  • Deepali Garg
  • Cheng-De Lin
  • Hana Tinch

Recent Publications

  1. C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “An IP-Agnostic Foundational Cell Array Offering Supply Chain Security,” The 61st Design Automation Conference, June 2024.

  2. C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2024.

  3. D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.

  4. D. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.

  5. B. Singer, A. Pandey, S. Li, L. Bauer, C. Miller, L. Pileggi, V. Sekar, Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations, IEEE Symposium on Security and Privacy, May 22-26, 2023.

  6. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.

  7. S. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra and L. Pileggi, “Split-Chip Design to prevent IP Reverse Engineering,” in IEEE Design & Test, doi: 10.1109/MDAT.2020.3033255.

  8. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.

  9. P. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.

  10. J. Sweeney, M.J.H. Heule, L. Pileggi, “Modeling Techniques for Logic Locking,” IEEE International Conference on Computer-Aided Design, November 2020.