An IP-Agnostic Foundational Cell Array Offering Supply Chain Security
C. Talbot, Deepali Garg, L. Pileggi and K. Mai, “An IP-Agnostic Foundational Cell Array Offering Supply Chain Security,” The 61st Design Automation Conference, June 2024.
IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpC. Talbot, Deepali Garg, L. Pileggi and K. Mai, “IP-Agnostic Standard Cell Fabric Offering Tamper Resistance and Supply Chain Resilience,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2024.
Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpD. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design
/in Integrated Circuits, Publications, Secure Hardware /by awpD. Garg, J. Sweeney and L. Pileggi, Quantifying the Efficacy of Logic Locking Methods, International Conference on VLSI Design, Kolkata India, January 2024.
Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations
/in Conference, Publications, Secure Hardware /by awpB. Singer, A. Pandey, S. Li, L. Bauer, C. Miller, L. Pileggi, V. Sekar, Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations, IEEE Symposium on Security and Privacy, May 22-26, 2023.
Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpP. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-Down Synthesis of Soft eFPGA Fabrics Using Standard ASIC Flows,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 29-April 1, 2021.
Split-Chip Design to prevent IP Reverse Engineering
/in Peer Reviewed, Publications, Secure Hardware /by awpS. Pagliarini, J. Sweeney, K. Mai, S. Blanton, S. Mitra and L. Pileggi, “Split-Chip Design to prevent IP Reverse Engineering,” in IEEE Design & Test, doi: 10.1109/MDAT.2020.3033255.
Top-down physical design of soft embedded FPGA fabrics
/in Integrated Circuits, Publications, Secure Hardware /by awpP. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Top-down physical design of soft embedded FPGA fabrics,” In proceedings of FPGA conference, Feb-March 2021.
Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion
/in Conference, Integrated Circuits, Publications, Secure Hardware /by awpP. Mohan, O. Atli, O. Kibar, M. Z. Vanaikar, L. Pileggi and K. Mai, “Hardware Redaction via Designer-Directed Fine-Grained Soft eFPGA Insertion,” In proceedings of Design and Test in Europe (DATE), February 1-5, 2021.
Modeling Techniques for Logic Locking
/in Conference, Publications, Secure Hardware /by pileggiJ. Sweeney, M.J.H. Heule, L. Pileggi, “Modeling Techniques for Logic Locking,” IEEE International Conference on Computer-Aided Design, November 2020.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774