Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees

M. Celik and L. T. Pileggi, “Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.

Bounds for BEM Capacitance Extraction

M. Beattie and L. T. Pileggi, “Bounds for BEM Capacitance Extraction”, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.

Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers

Rohini Gupta, John Willis and L.T. Pileggi, “Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers”, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.

PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm

A. Odabasioglu, M. Celik and L. T. Pileggi, “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.

Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler

M. Celik and L. T. Pileggi, “Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.

A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing

N. Menezes, R. Baldick and L.T. Pileggi, “A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing”, IEEE Transactions on Computer- Aided Design, August 1997.

Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets

S. Pullela, N. Menezes and L.T. Pileggi, “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.

Transmission Line Synthesis via Constrained Multivariable Optimization

Rohini Gupta, Byron Krauter and Lawrence Pileggi, “Transmission Line Synthesis via Constrained Multivariable Optimization”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.

The Elmore Delay as a Bound for RC Trees with Generalized Input Signals

Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.