Publications – Page 6 – Larry Pileggi

Latch-Based Logic Locking

January 30, 2020/in Conference, Publications, Secure Hardware /by awp

J. Sweeney, M. Zackriya, S. Pagliarini, and L. Pileggi, “Latch-Based Logic Locking,” Government Microcircuit Applications and Critical Technology Conference (GOMACTech), March 2020.

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

January 30, 2020/in Conference, Integrated Circuits, Publications /by awp

M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)

Steady-State Simulation for Combined Transmission and Distribution Systems

January 30, 2020/in Conference, Power Systems, Publications /by awp

A. Pandey and L. Pileggi, “Steady-State Simulation for Combined Transmission and Distribution Systems,” in IEEE Transactions on Smart Grid, August 2019. (DOI: 10.1109/TSG.2019.2932403)

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

January 30, 2020/in Conference, Integrated Circuits, Publications /by awp

S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography

January 29, 2020/in Publications, Secure Hardware /by awp

I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, (DOI: 10.1007/s41635-019-00080-y).

Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization

August 9, 2019/in Conference, Integrated Circuits, Publications /by awp

F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.

Latch-Based Logic Locking

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

Steady-State Simulation for Combined Transmission and Distribution Systems

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography

Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization

A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks

A Linear Formulation for Power System State Estimation including RTU and PMU Measurements

Robust Sequential Steady-State Analysis of Cascading Outages

Implicitly Modeling Frequency Control with Power Flow

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