Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling
Florin Dartu and Lawrence Pileggi, “Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling”, Proceedings of the Design Automation Conference, 1997.
EWA: Exact Wire Sizing Algorithm
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpR. Kay, G. Bucheuv, and L. Pileggi, “EWA: Exact Wire Sizing Algorithm”, 1997 International Symposium on Physical Design, April 1997.
A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpG. Ellis, L. Pileggi and R. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
A Sparse Macromodeling Method for RC Interconnect Multiports
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpF. Liu, L. Pileggi and A.J. Strojwas, “A Sparse Macromodeling Method for RC Interconnect Multiports”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpS. Pullela, N. Menezes and L.T. Pileggi, “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.
Transmission Line Synthesis via Constrained Multivariable Optimization
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpRohini Gupta, Byron Krauter and Lawrence Pileggi, “Transmission Line Synthesis via Constrained Multivariable Optimization”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
/0 Comments/in Electronic Design Automation, Peer Reviewed, Publications /by awpRohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.
Gate-level modeling of of coupling capacitance effects
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpF. Dartu and L.T. Pileggi, “Gate-level modeling of of coupling capacitance effects”, Proceedings of the SRC Techcon Conference, October 1996.
Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpFlorentin Dartu and Lawrence T. Pileggi, “Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models”, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
RC-Interconnect Macromodels for Timing Simulation
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpFlorin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, “RC-Interconnect Macromodels for Timing Simulation”, Proceedings of the Design Automation Conference , 1996.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774