A. Mehta, Y-P. Chen, N. Menezes, L. T.Pileggi and M. Wong, “Clustering and Load Balancing for Buffered Clock Tree Synthesis”, Proceedings of the Int’l Conference on Computer Design, October 1997.
Ravishankar Arunachalam, Florentin Dartu and Lawrence T.Pileggi, “CMOS Gate Delay Models for General RLC Loading”, Proceedings of the Int’l Conference on Computer Design, October 1997.
John He, Mustafa Celik and Lawrence Pileggi, “SPIE: Sparse PEEC Inductance Extraction”, Proceedings of the Design Automation Conference, 1997.
Michael Beattie and Lawrence Pileggi, “Bounds for BEM Capacitance Extraction”, Proceedings of the Design Automation Conference, 1997.
Florin Dartu and Lawrence Pileggi, “Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling”, Proceedings of the Design Automation Conference, 1997.
R. Kay, G. Bucheuv, and L. Pileggi, “EWA: Exact Wire Sizing Algorithm”, 1997 International Symposium on Physical Design, April 1997.
G. Ellis, L. Pileggi and R. Rutenbar, “A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
F. Liu, L. Pileggi and A.J. Strojwas, “A Sparse Macromodeling Method for RC Interconnect Multiports”, Proceedings of the Custom Integrated Circuits Conference, May 1997.
S. Pullela, N. Menezes and L.T. Pileggi, “Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.
Rohini Gupta, Byron Krauter and Lawrence Pileggi, “Transmission Line Synthesis via Constrained Multivariable Optimization”, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774