An 8-bit 1.5GS/s Flash ADC Using Post-Manufacturing Statistical Selection

J. Proesel, G. Keskin, J.O. Plouchart and L. Pileggi, “An 8-bit 1.5GS/s Flash ADC Using Post-Manufacturing Statistical Selection”, Int’l Custom Integrated Circuits Conference, Sept. 2010.

Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing

A. Bonnoit, S. Herbert and L. Pileggi, “Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing”, International Symposium on Low Power Electronics and Design, August 2010.

Modeling of Statistical Element Selection Based Self-Healing Analog Circuits

G. Keskin, J. Proesel and L. Pileggi, “Modeling of Statistical Element Selection Based Self-Healing Analog Circuits”, Proceedings of the SRC Techcon Conference, September 2010.

 

Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs

D. Morris, S. Rovner, L. Pileggi, A. Strojwas and K. Vaidyanathan, “Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs”, IEEE Symposium on VLSI (Invited Presentation), June 2010.

Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, Invited Keynote Paper

Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry Pileggi, Andrzej Strojwas, Jason D. Hibbeler, “Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, Invited Keynote Paper”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, April 2010.

Demonstrating the benefits of template-based design-technology co-optimization

L. Liebmann, J. Hibbeler, N. Hieter, L. Pileggi, M. Moe, T. Jhaveri, V. Rovner, “Demonstrating the benefits of template-based design-technology co-optimization”, SPIE Advanced Lithography Conference, February 2010.

Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization

T. Jhaveri, U. Urslan, V. Rovner, L. Pileggi & A. J. Strojwas, “Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization”, SPIE Advanced Lithography Conference, Selected for Keynote Presentation, February 2010.

Integrating Dynamic Voltage/Frequency Scaling and Adaptive Body Biasing using Test-time Voltage Selection

A. Bonnoit, S. Herbert, L. Pileggi and D. Marculescu, “Integrating Dynamic Voltage/Frequency Scaling and Adaptive Body Biasing using Test-time Voltage Selection”, International Symposium on Low Power Electronics and Design, August 2009.

An 8-bit Flash ADC using Statistical Element Selection

J. Proesel, G. Keskin and L. Pileggi, “An 8-bit Flash ADC using Statistical Element Selection”, Proceedings of the SRC Techcon Conference, September 2009.

An SRAM Design Framework for Deeply-Scaled CMOS

U. Arslan, J. Wang and L. Pileggi, “An SRAM Design Framework for Deeply-Scaled CMOS”, Proceedings of the SRC Techcon Conference, September 2009.