An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI
V. H.-C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI”, in IEEE Symp. VLSI Circuits, June 2013.
A Linearized Low Noise VCO-Based PLL With Automatic Biasing
/0 Comments/in Integrated Circuits, Peer Reviewed, Publications /by awpB. Sadhu, M.A. Ferriss, A.S. Natarajan, S. Yaldiz, J-O. Plouchart, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, A. Babakhani, S. Reynolds, X. Li, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A Linearized Low Noise VCO-Based PLL With Automatic Biasing”, IEEE Journal of Solid State Circuits (Invited), Volume 48 , Issue 5, May 2013.
All-Magnetic, Nonvolatile, Addressable Chainlink Memory
/0 Comments/in Integrated Circuits, Peer Reviewed, Publications /by awpD. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic
/0 Comments/in Integrated Circuits, Peer Reviewed, Publications /by awpV. Sokalski, D. Bromberg, D. Morris, M. T. Moneck, E. Yang, L. Pileggi, and J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
Rethinking ASIC design with next-generation lithography and process integration
/0 Comments/in Conference, Integrated Circuits, Publications /by awpK. Vaidyanathan, L. Liebmann and L. Pileggi, “Rethinking ASIC design with next-generation lithography and process integration”, SPIE Advanced Lithography Conference, February 2013.
Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic
/0 Comments/in Conference, Integrated Circuits, Publications /by awpV. Sokalski, D.M. Bromberg, D. Morris, M.T. Moneck, E. Yang, L. Pileggi, J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic”, 12th Joint MMM/Intermag Conference, January 2013.
All-Magnetic, Nonvolatile, Addressable Chainlink Memory
/0 Comments/in Conference, Integrated Circuits, Publications /by awpD. Bromberg, D. Morris, L. Pileggi and J. Zhu, “All-Magnetic, Nonvolatile, Addressable Chainlink Memory”, 12th Joint MMM/Intermag Conference, January 2013.
Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography
/in Conference, Integrated Circuits, Publications /by awpQ. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
/0 Comments/in Conference, Integrated Circuits, Publications /by awpJ.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.
Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction
/0 Comments/in Conference, Electronic Design Automation, Integrated Circuits, Publications /by awpQ. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774