From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography

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I. Karageorgos, M. Isgenc, S. Pagliarini, and L. Pileggi, Chip-to-chip Authentication Method based on SRAM PUF and Public Key Cryptography, Journal of Hardware and Systems Security, November 2019 (DOI: 10.1007/s41635-019-00080-y).

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes

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M. Isgenc, M. Martins, S. Pagliarini and L. Pileggi, “Logic IP for Low-Cost IC Design in Advanced CMOS Nodes,” IEEE Transactions on Very Large Scale Integration, Vol 28, Issue 2, February 2020. (DOI:10.1109/TVLSI.2019.2942825.)

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, Issue 2, February 2020. DOI (10.1109/TCAD.2018.2889772)

Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization

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F. Sadi , Joe Sweeney, T. M. Low, J. C. Hoe, L. Pileggi, F. Franchetti, “Efficient SpMV operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization,” IEEE/ACM International Symposium on Microarchitecture, October 2019.

A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks

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S. Pagliarini, S. Bhuin, M. Isgenc, A. Biswas, L. Pileggi, A Probabilistic Synapse with Strained MTJs for Spiking Neural Networks, IEEE Transactions on Neural Networks and Learning Systems, June 2019.

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.

From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration

/in , , /by

S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “From Virtual Characterization to Test-Chips: DFM Analysis through Pattern Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, December 2018.

Application and Product-Volume Specific Customization of BEOL Metal Pitch

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S. Pagliarini, M. Isgenc, M. Martins and L. Pileggi, “Application and Product-Volume Specific Customization of BEOL Metal Pitch,” IEEE Transactions on VLSI, Vol. 26, Issue:9, pp. 1627-1636, September 2018.

An Oscillatory Neural Network with Programmable Resistive Synapses

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T. Jackson, S. Pagliarini and L. Pileggi, “An Oscillatory Neural Network with Programmable Resistive Synapses,” in 28 nm CMOS, IEEE International Conference on Rebooting Computing, November 2018.