On-Package Decoupling Optimization with Package Macromodels
H. Zheng, B. Krauter, L. Pileggi, “On-Package Decoupling Optimization with Package Macromodels”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)
/0 Comments/in Conference, Integrated Circuits, Publications /by awpK.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics
/0 Comments/in Conference, Integrated Circuits, Publications /by awpA. Koorapaty, L. Pileggi, H. Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics”, International Conference on Field Programmable Logic and Applications, September 2003.
An Architecture Exploration of Via Patterned Gate Arrays
/0 Comments/in Conference, Electronic Design Automation, Integrated Circuits, Publications /by awpC. Patel, A. Cozzie, H. Schmit and L. Pileggi, “An Architecture Exploration of Via Patterned Gate Arrays”, Internation Symposium on Physical Design, April 2003.
Heterogeneous Programmable Logic Block Architectures
/0 Comments/in Conference, Integrated Circuits, Publications /by awpA. Koorapaty, V. Chandra, K.Y. Tong, C. Patel, L. Pileggi and H. Schmit, “Heterogeneous Programmable Logic Block Architectures”, Design and Test in Europe Conference (DATE), March 2003.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774